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| integrated module products logic devices incorporated www.logicdevices.com 1 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product ddr3 integrated module [imod]: x 9 dd 9 dd 4 9 ? 9 r u / 2 : 3 2 : ( 5 9 dd 9 dd 4 9 ? 9 x 9 r u 9 f h q w h u w h u p l q d w h g push/pull output x 3 d f n d j h p p [ p p [ p p [ p d w u l [ z e d o o v x 0 d w u l [ e d o o s l w f k p p 6 s d f h v d y l q j i r r w s u l q w 7 k h u p d o o \ h q k d q f h g , p s h g d q f h p d w f k h g l q w h j u d w h g s d f n d j l q j ' l i i h u h q w l d o e l g l u h f w l r q d o g d w d v w u r e h q e l w s u h i h w f k d u f k l w h f w x u h l q w h u q d o e d q n v s h u z r u g z r u g v l q w h j u d w h g l q s d f n d j h 1 r p l q d o d q g g \ q d p l f r q g l h w h u p l q d - w l r q 2 ' 7 i r u g d w d v w u r e h d q g p d v n signals. 3 u r j u d p p d e o h & $ 6 5 ( $ ' o d w h q f \ & / d q g & $ 6 : 5 , 7 ( o d w h q f \ & : / features 9, and 11 ) l [ h g e x u v w o h q j w k % / r i d q g e x u v w f k r s % & r i 6 h o h f w d e o h % & r u % / r q w k h i o \ 2 7 ) 6 h o i $ x w r 5 h i u h v k p r g h v 2 s h u d w l q j 7 h p s h u d w x u h 5 d q j h d p e l h q w w h p s 7 $ x & r p p h u f l d o ? & w r ? & x , q g x v w u l d o ? & w r ? & v x s s r u w l q j 6 ( / ) $ 8 7 2 5 ( ) 5 ( 6 + x ( [ w h q g h g ? & w r ? & p d q x d o 5 ( ) 5 ( 6 + r q o \ x 0 l o 7 h p s ? & w r ? & p d q x d o 5 ( ) 5 ( 6 + r q o \ & 2 5 ( f o r f n l q j i u h t x h q f l h v 0 + ] ' d w d 7 u d q v i h u 5 d w h v 0 e s v : u l w h o h y h o l q j multipurpose register 2 x w s x w ' u l y h u & d o l e u d w l r q v s d f h v d y l q j v z k l o h s u r y l g - l q j d v x u i d f h p r x q w i u l h q g o \ s l w f k p p 5 h g x f h g , 2 u r x w l q j 5 h g x f h g w u d f h o h q j w k v g x h w r w k h k l j k o \ l q w h j u d w h g l p s h g d q f h p d w f k h g s d f n d j l q j + l j k 7 & ( r u j d q l f o d p l q d w h l q w h u - s r v h u i r u l p s u r y h g j o d v v v w d e l o l w \ r y h u d z l g h r s h u d w l q j w h p s h u d w x u h 6 x l w d e l o l w \ r i x v h l q + l j k 5 h o l d e l o l w \ d s s o l f d w l r q v u h t x l u l q j 0 l o w h p s q r q k h u p h w l f g h y l f h r s h u d w l r q benefits
1 r w h 7 k l v l q w h j u d w h g s u r g x f w d q g r u l w v v s h f l i l f d w l r q v d u h v x e m h f w w r f k d q j h z l w k r x w q r w l f h / d w h v w g r f x p h q w v k r x o g e h u h w u l h y h g i u r p / ' , s u l r u w r \ r x u g h v l j q f r q v l g h u d w l r q o rder n umber s peed g rade p kg f ootprint i/o p itch p kg n o . p p [ p p imod part information bg2 p p ddr3-1866 ddr3-1600 ddr3-1333 ddr3-1866 ddr3-1600 ddr3-1333 / ' 0 6 % * [ / ' 0 6 % * [ / ' 0 6 % * [ / ' 0 6 % * [ l9d3256m80sbg2x125 l9d3256m80sbg2x15 preliminar p p k k g g f f oo oo t na na na na in in min min ry information q x d o x d o h v v v j ose register e register w ' u l y h u u l & d o l e u d d o l e u d q j w k v q j w k v g x h g x w r j u d w h g d w l p s h g d l p s h g d d f n d j l q j f n d j l q j ( ( r u j d q l f r u j d q l f o d p o d p i r u i r u l p s u r y h g l p s u r y h g h u h u d d z l g h r s h u r s h 6 x l w d e l o l w \ 6 x l w d e l o l w \ r i r i d s s o l f d w l r q d s s o l f d w k h u p h w k h u p h w ry eliminar ar mi mi lim lim lim lim 16 dr3-1333 r3-186 ddr3-1 dr
sample part number: l9d3256mxxsbg2 word = 256mb speed grade 1.5ns / 667mhz 1.25ns / 800mhz 1.07ns / 933mhz 15 125 107 256m l9d3 temperature industrial (-40 o c to 85 o c) extended (-40 o c to 105 o c) military (-55 o c to 125 o c) i e m note: not all options can be combined. please see our part catalog for available offerings. xxs bg2 ddr3 imod wordwidth x72 x80 s = single channel 16 x 22mm pbga code code x xxx commercial (0 o c to 70 o c) c x voltage 1.35v 1.5v l - code logic devices incorporated www.logicdevices.com 2 july 24, 2013 lds-l9d3256mxxsbg2 rev b 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 high performance, integrated memory module product features f igure 1 - ddr3 p art n umbers & r q i l j x u d w l r q 5 h i u h v k & r x q w 5 2 : $ g g u h v v l q j % d q n $ g g u h v v l q j & r o x p q $ g g u h v v l q j > 0 h j [ e d q n v [ @ [ 8k . $ > @ $ > @ % $ > @ . $ > @ parameter 256 meg x 72/80 t able 1: a ddressing bank active reading writing activating refreshing self refresh idle active power- down zq calibration from any state power applied reset procedure power on initialization mrs, mpr, write leveling preharge power- down writing automatic sequence command sequence preharging read read read read ap read ap read ap pre, prea pre, prea pre, prea write write cke l cke l cke l write write ap write ap write ap pde pde pdx pdx srx sre ref mrs act reset zqcl zqcl/zqcs reading act = activate prea=precharge all srx = self refresh exit mpr = multipurpose register read = rd, rds4, rds8 write = wr, wrs4, wrs8 mrs = mode register set read ap = rdap, rdaps4, rdaps8 write ap = wrap, wraps4, wraps8 pde = power-down entry ref = refresh zqcl = zq long calibration pdx = power-down exit reset = start reset procedure zqcs = zq short calibration pre = precharge sre = self refresh entry logic devices incorporated www.logicdevices.com 3 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product state diagram f igure 2 - s implified s tate d iagram logic devices incorporated www.logicdevices.com 4 july 24, 2013 lds-l9d3256mxxsbg2 rev b 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 high performance, integrated memory module product 7 k h ' ' 5 6 ' 5 $ 0 x v h v g r x e o h g d w d u d w h d u f k l w h f w x u h w r d f k l h y h k l j k v s h h g r s h u d w l r q 7 k h g r x e o h g d w d u d w h ' ' 5 d u f k l w h f w x u h l v d q q s u h i h w f k z l w k d q l q w h u i d f h g h v l j q h g w r w u d q v i h u w z r g d w d z r u g v s h u f o r f n f \ f o h d w w k h , 2 s l q v $ v l q j o h 5 ( $ ' r u : 5 , 7 ( d f f h v v i r u w k h ' ' 5 6 ' 5 $ 0 f r q v l v w v r i d v l q j o h q e l w z l g h r q h f o r f n f \ f o h g d w d w u d q v i h u d w w k h l q w h u q d o p h p r u \ f r u h d q g h l j k w f r u u h v s r q g l q j q e l w z l g h r q h k d o i f o r f n f \ f o h g d w d w u d q v i h u at the i/o pin. 7 k h g l i i h u h q w l d o v w u r e h v ' 4 6 [ ' 4 6 [ ? d u h w u d q v p l w w h g h [ w h u q d o o \ d o r q j z l w k g d w d i r u x v h l q g d w d f d s w x u h d w w k h ' ' 5 6 ' 5 $ 0 l q s x w u h f h l y h u ' 4 6 l v f h q w h u d o l j q h g z l w k g d w d i r u : 5 , 7 ( v 7 k h 5 ( $ ' g d w d l v w u d q v p l w w h g e \ w k h ' ' 5 6 ' 5 $ 0 d q g h g j h d o l j q h g w r w k h g d w d v w u r e h v 7 k h ' ' 5 6 ' 5 $ 0 r s h u d w h v i u r p d g l i i h u h q w l d o f o r f n & . [ & . [ ? 7 k h f u r v v l q j r i & . j r l q j + , * + d q g & . ? j r l q j / 2 : l v u h i h u u h g w r d v w k h s r v l - w l y h h g j h r i & o r f n & . & r q w u r o & r p p d q g d q g $ g g u h v v v l j q d o v d u h u h j- l v w h u h g d w h y h u \ s r v l w l y h h g j h r i & . , q s x w g d w d l v u h j l v w h u h g r q w k h i l u v w u l v l q j h g j h r i ' 4 6 d i w h u w k h : 5 , 7 ( s u h d p e o h d q g r x w s x w g d w d l v u h i h u - h q f h g r q w k h i l u v w u l v l q j h g j h r i ' 4 6 d i w h u w k h 5 ( $ ' s u h d p e o h 5 ( $ ' d q g : 5 , 7 ( d f f h v v h v w r w k h ' ' 5 6 ' 5 $ 0 d u h e x u v w r u l h q w h g $ f f h v v h v v w d u w d w d v h o h f w h g o r f d w l r q d q g f r q w l q x h i r u d s u r j u d p p h g q x p e h u r i o r f d w l r q v l q d s u r j u d p p h g v h t x h q f h $ f f h v v h v e h j l q z l w k w k h u h j l v w u d w l r q r i d q $ & 7 , 9 $ 7 ( f r p p d q g z k l f k l v w k h q i r o o r z h g e \ d 5 ( $ ' r u : 5 , 7 ( f r p p d q g 7 k h d g g u h v v e l w v u h j l v w h u h g f r l q f l g h q w z l w k w k h $ & 7 , - 9 $ 7 ( f r p p d q g d u h x v h g w r v h o h f w w k h e d q n d q g w k h v w d u w l q j f r o x p q o r f d - w l r q i r u w k h e x u v w d f f h v v ' ' 5 6 ' 5 $ 0 g h y l f h v x v h 5 ( $ ' d q g : 5 , 7 ( % / d q g % & $ q $ 8 7 2 3 5 ( & + $ 5 * ( i x q f w l r q p d \ e h h q d e o h g w r s u r y l g h d v h o i w l p h g 5 2 : 3 5 (- & + $ 5 * ( w k d w l v l q l w l d w h g d w w k h h q g r i w k h e x u v w d f f h v v $ v z l w k v w d q g d u g ' ' 5 6 ' 5 $ 0 g h y l f h v w k h s l s h o l q h g p x o w l e d q n d u f k l w h f - w x u h r i w k h ' ' 5 6 ' 5 $ 0 d o o r z v i r u f r q f x u u h q w r s h u d w l r q w k h u h e \ s u r y l g - l q j k l j k e d q g z l g w k e \ k l g l q j 5 2 : 3 5 ( & + $ 5 * ( d q g $ & 7 , 9 $ 7 , 2 1 w l p h $ 6 ( / ) 5 ( ) 5 ( 6 + p r g h l v s u r y l g h g i r u d o o w h p s h u d w x u h j u d g h r i i h u l q j v d o r q j z l w k $ 8 7 2 6 ( / ) 5 ( ) 5 ( 6 + i r u , q g x v w u l d o s u r g x f w d v z h o o d v s r z h u v d y l q j 3 2 : ( 5 ' 2 : 1 p r g h functional description i ndustrial t emperature 7 k h l q g x v w u l d o w h p s h u d w x u h , g h y l f h u h t x l u h v w k h d p e l h q w w h p s h u d w x u h q r w h [ f h h g ? & r u ? & - ( ' ( & v s h f l i l f d w l r q v u h t x l u h w k h 5 ( ) 5 ( 6 + u d w h w r g r x e o h z k h q 7 $ h [ f h h g v ? & w k l v d o v r u h t x l u h v x v h r i w k h k l j k w h p s h u d w x u h 6 ( / ) 5 ( ) 5 ( 6 + r s w l r q $ g g l w l r q d o o \ 2 ' 7 u h v l v w d q f h d q g w k h , 1 3 8 7 2 8 7 3 8 7 l p s h g d q f h p x v w e h g h u d w h g z k h q w k h 7 $ is <0 ? & r u ! ? & e xtended t emperature 7 k h ( [ w h q g h g w h p s h u d w x u h ( g h y l f h u h t x l u h v w k h d p e l h q w w h p s h u d w x u h q r w h [ f h h g ? & r u ? & - ( ' ( & v s h f l i l f d w l r q v u h t x l u h w k h u h i u h v k u d w h w r g r x e o h z k h q 7 $ h [ f h h g v ? & w k l v d o v r u h t x l u h v x v h r i w k h k l j k w h p s h u d w x u h 6 ( / ) 5 ( ) 5 ( 6 + r s w l r q $ g g l w l r q d o o \ 2 ' 7 u h v l v w d q f h d q g w k h , 1 3 8 7 2 8 7 3 8 7 l p s h g d q f h p x v w e h g h u d w h g z k h q w k h 7 $ is <0 ? & or >85 ? & m ilitary , e xtreme o perating t emperature 7 k h 0 l o 7 h p s 0 g h y l f h u h t x l u h v w k h d p e l h q w w h p s h u d w x u h q r w h [ f h h g -55 ? & r u ? & - ( ' ( & u h t x l u h v w k h 5 ( ) 5 ( 6 + u d w h g r x e o h z k h q 7 $ h [ f h h g v ? & d q g / ' , u h f r p p h q g v d q d g g l w l r q d o g h u d w l q j d v v s h f l i l h g l q w k l v g r f x p h q w d v w r s u r s h u o \ p d l q w d l q w k h ' 5 $ 0 f r u h f h o o f k d u j h d w w h p s h u d w x u h v d e r y h 7 $ >105 ? & d4 ba clk\ clk cke cas\ ras\ we\ odt reset\ cs\ a 14-a0 a dq 15 dq 8 dq 7 dq 0 d3 dq 15 dq 8 dq 7 dq 0 d2 dq 15 dq 8 dq 7 dq 0 d1 dq 15 dq 8 dq 7 dq 0 cs\ reset\ odt we\ ras\ cas\ cke clk clk\ d0 dq 15 dq 8 dq 7 dq 0 dq 15 dq 8 dq 7 dq 0 dm 1 dm 0 dqs1, dqs1\ dqs0, dqs0\ dq 31 dq 24 dq 23 dq 16 dqs3, dqs3\ dqs2, dqs2\ dq 47 dq 40 dq 39 dq 32 dqs5, dqs5\ dqs4, dqs4\ dq 63 dq 56 dq 55 dq 48 dqs7, dqs7\ dqs6, dqs6\ dq 79 dq 72 dq 71 dq 64 dqs9, dqs9\ dqs8, dqs8\ dm 3 dm 2 dm 5 dm 4 dm 7 dm 6 dm 9 dm 8 b a2-0 a ba clk\ clk cke cas\ ras\ we\ odt reset\ cs\ ba clk\ clk cke cas\ ras\ we\ odt reset\ cs\ a ba clk\ clk cke cas\ ras\ we\ odt reset\ cs\ a ba clk\ clk cke cas\ ras\ we\ odt reset\ cs\ a zq vssq 240 1% vssq zq vssq zq vssq zq vssq zq logic devices incorporated www.logicdevices.com 5 july 24, 2013 lds-l9d3256mxxsbg2 rev b 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 high performance, integrated memory module product f igure 3 - f unctional b lock d iagram v dd vssq vss v dd q vssq v dd v dd q vssq vss v dd v dd q vssq v dd q dm8 dq68 dq71 dqs8# dq65 dq66 dq72 dqs9 dq75 dq78 dq77 dm9 dq70 dq69 dqs8 dq67 dq64 dq74 dqs9# dq73 dq76 dq79 vss v dd q v dd vssq v dd q vss vssq v dd q v dd vssq v dd q vss vssq dm6 dq52 dq55 dqs6# dq49 dq50 dq56 dqs7 dq59 dq62 dq61 vss dm7 dq54 dq53 dqs6 dq51 dq48 dq58 dqs7# dq57 dq60 dq63 v dd vssq vss v dd q vssq v dd v dd q vssq vss v dd v dd q vssq v dd q a14 a11 v dd a1 ba2 vss v dd vss v dd vss vss a13 a7 a4 a3 ba0 cs# odt clk# cas# v dd vrefdq v ss a8 a6 a5 a12 ba1 we# cke clk ras# v ss reset# a9 a2 vss a0 a10 v dd vss v dd vss v dd v dd vrefca vss v dd q v dd vssq v dd q vss vssq v dd q v dd vssq v dd q vss vssq v dd dm4 dq36 dq39 dqs4# dq33 dq34 dq40 dqs5 dq43 dq46 dq45 dm5 dq38 dq37 dqs4 dq35 dq32 dq42 dqs5# dq41 dq44 dq47 v dd vssq vss v dd q vssq v dd v dd q vssq vss v dd v dd q vssq v dd q dm2 dq20 dq23 dqs2# dq17 dq18 dq24 dqs3 dq27 dq30 dq29 dm3 dq22 dq21 dqs2 dq19 dq16 dq26 dqs3# dq25 dq28 dq31 vss v dd q v dd vssq v dd q vss vssq v dd q v dd vssq v dd q vss vssq dm0 dq4 dq7 dqs0# dq1 dq2 dq8 dqs1 dq11 dq14 dq13 dm1 dq6 dq5 dqs0 dq3 dq0 dq10 dqs1# dq9 v dd vssq vss v dd q vssq v dd v dd q vssq vss 12345678910111213 a a b b c c d d e e f f g g h h j j k k l l m m n n p p r r t t 12345678910111213 address unpopulated level ref v + (i/o power) cntrl gnd (core) data io v dd u v w y aa u v w y aa v dd q gnd (i/o) v + (core power) 271bga-1.00mm pitch - x72/80, scb vssq v dd q dq12 dq15 v dd logic devices incorporated www.logicdevices.com 6 july 24, 2013 lds-l9d3256mxxsbg2 rev b 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 high performance, integrated memory module product f igure 4 - sdram - ddr3 p inout t op v iew ball /signal location (pbga) logic devices incorporated www.logicdevices.com july 24, 2013 lds-l9d3256mxxsbg2 rev b 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 high performance, integrated memory module product t able 2 - b all /s ignal l ocation and d escription ball assignments symbol type description l10, p10, l12, n10, n11, m22, m12, n12, m13, l13, l9, p12, m10, n13, p13 n9, m9, p9 m6, n6 0 n8 & % ) ( - + 8 7 < : m5 n5 m8 a 0, a 1, a 2, a 3, a 4, a 5, a 6, a 7, a 8, a 9, a 10 /ap, a 11, a 12 / bc, a 13, a 14 ba 0 , ba 1, ba 2 clk x , clk x \ cke cs\ dmx ras\ cas\ we\ input input input input input input input input input address inputs: 3 u r y l g h w k h 5 2 : d g g u h v v i r u $ & 7 , 9 $ 7 ( f r p p d q g v d q g w k h f r o x p q d g g u h v v d q g d x w r s u h f k d u j h e l w $ 10 i r u 5 ( $ ' < : 5 , 7 ( f r p p d q g v w r v h o h f w r q h o r f d w l r q r x w r i w k h p h p r u \ d u u d \ l q w k h u h v s h f w l y h e d q n $ 10 v d p s o h g g x u l q j d 3 5 ( & + $ 5 * ( f r p p d q g g h w h u p l q h v z k h w k h u w k h 3 5 ( & + $ 5 * ( d s s o l h v w r r q h e d q n $ 10 / 2 : e d q n v h o h f w h g e \ % $ > @ r u d o o e d q n v $ 10 + , * + 7 k h d g g u h v v l q s x w v d o v r s u r y l g h w k h r s f r g h g x u l q j d / 2 $ ' 0 2 ' ( f r p p d q g $ g g u h v v l q s x w v d u h u h i h u h q f h g w r 9 u h i & $ $ 12 % & z k h q h q d e o h g l q w k h p r g h u h j l v w h u 0 5 $ 12 l v v d p s o h g g x u l q j 5 ( $ ' d q g : 5 , 7 ( f r p p d q g v w r g h w h u p l q h z k h w k h u e x u v w f k r s / 2 : % & 4 e x u v w f k r s bank address inputs: % $ > @ g h i l q h w k h e d q n w r z k l f k d q $ & 7 , 9 $ 7 ( 5 ( $ ' : 5 , 7 ( r u 3 5 ( & + $ 5 * ( f r p p d q g l v e h l q j d s s o l h g % $ > @ g h i l q h z k l f k p r g h u h j l v w h u 0 5 0 , mr 1 , mr 2 , or mr 3 l v o r d g h g g x u l q j w k h / 2 $ ' 0 2 ' ( f r p p d q g % $ > @ d u h u h i h u h q f h g w r 9 u h i & $ clock: & . [ d q g & . [ ? d u h g l i i h u h q w l d o f o r f n l q s x w v r q h g l i i h u h q w l d o s d l u s h u : 2 5 ' i r x u : 2 5 ' v f r q w d l q h g l q w k h / ' [ [ * s u r g x f w $ o o f r q w u r o d q g d g g u h v v l q s x w v l j q d o v d u h v d p s o h g r q w k h f u r v v l q j r i w k h s r v l w l y h h g j h r i & . [ d q g w k h q h j d w l y h h g j h r i & . [ ? 2 x w s x w g d w d v w u r e h v 8 ' 4 6 [ 8 ' 4 6 [ ? d q g / ' 4 6 [ / ' 4 6 [ ? l v u h i h u h q f h g w r w k h f u r v v l q j r i & . [ d q g & . [ ? clock enable: & . ( h q d e o h v d q g g l v d e o h v l q w h u q d o f l u f x l w u \ d q g f o r f n v r q w k h 6 ' 5 $ 0 7 k h v s h f l i l f f l u f x l w u \ w k d w l v h q d e o h g g l v d e o h g l v g h s h q g h q w x s r q w k h ' ' 5 6 ' 5 $ 0 f r q i l j x u d w l r q d q g r s h u d w l q j p r g h 7 d n l q j & . ( / 2 : s u r y l g h v 3 5 ( & + $ 5 * ( s r z h u g r z q d q g 6 ( / ) 5 ( ) 5 ( 6 + r s h u d w l r q v d o o e d q n v l g o h r u d f w l y h s r z h u g r z q u r z d f w l y h l q d q \ e d q n & . ( l v v \ q f k u r q r x v i r u s r z h u g r z q h q w u \ d q g h [ l w d q g i r u v h o i u h i u h v k h q w u \ & . ( l v d v \ q f k u r q r x v i r u v h o i u h i u h v k h [ l w , q s x w e x i i h u v h [ f o x g l q j & . [ & . [ ? & . ( 5 ( 6 ( 7 d q g 2 ' 7 d u h g l v d e o h g g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + & . ( l v u h i h u h q f h g w r 9 u h i & $ chip select: & 6 ? h q d e o h v u h j l v w h u h g / 2 : d q g g l v d e o h v w k h f r p p d q g g h f r g h u $ o o f r p p d q g v d u h p d v n h g z k h q & 6 ? l v u h j l v w h u h g + , * + & 6 ? s u r y l g h v i r u h [ w h u q d o u d q n v h o h f w l r q r q v \ v w h p v z l w k p x o w l s o h u d q n v & 6 ? l v f r q v l g h u h g s d u w r i w k h f r p p d q g f r g h & 6 ? l v u h i h u h q f h g w r 9 u h i & $ input data mask: ' 0 [ l v w k h e \ h z l g h g d w d p d v n i r u w k h u h v s h f w l y h e l w g d w d i l h o g v 7 k h g d w d p d v n l q s x w p d v n v : 5 , 7 ( g d w d % \ w h g d w d v p d v n h g z k h q ' 0 [ l v v d p s o h g + , * + 7 k h ' 0 [ s l q v d u h l q s x w v r q o \ w k h s l q v h o h f w u l f d o o r d g l q j l v g h v l j q h g w r p d w f k w k d w r i w k h ' 4 ' 4 6 [ d q g ' 4 6 [ ? pins. row address strobe/select: ' h i l q h v w k h f r p p d q g e h l q j h q w h u h g d o r q j & $ 6 ? : ( ? d q g & 6 ? 7 k l v l q s x w s l q l v u h i h u h q f h g w r 9 u h i & $ column address strobe/select: ' h i l q h v w k h f r p p d q g e h l q j h q w h u h g d o r q j z l w k 5 $ 6 ? : ( ? d q g & 6 ? 7 k l v l q s x w s l q l v u h i h u h q f h g w r 9 u h i & $ write enable input: ' h i l q h v w k h f r p p d q g e h l q j h q w h u h g d o r q j z l w k & $ 6 ? 5 $ 6 ? d q g & 6 ? 7 k l v l q s x w s l q l v u h i h u h q f h g w r 9 u h i & $ logic devices incorporated www.logicdevices.com 8 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 2 - b all /s ignal l ocation and d escription c ontinued ball assignments symbol type description 1 m3 % & & % ( ) ) ( + - - + 7 8 8 7 : < < : % & & & & % % & & % % & % & & % ( ) ) ( ) ( ( ) ) ( ( ) ( ) f2, f3 + - - + - + + - - + + - + - - + odt reset\ dqsx, dqsx\ dq 0, dq 1, dq 2, dq 3, dq 4, dq 5, dq 6, dq 7 dq 8, dq 9, dq 10, dq 11, dq 12, dq 13, dq 14, dq 15 dq 16, dq 17, dq 18, dq 19, dq 20, dq 21, dq 22, dq 23 dq 24, dq 25, dq 26, dq 27, dq 28, dq 29, dq 30, dq 31 dq 32, dq 33, dq 34, dq 35, dq 36, dq 37, dq 38, dq 39 dq 40, dq 41, dq 42, dq 43, dq 44, dq 45, dq 46, dq 47 input input input i/o i/o i/o i/o i/o i/o on-die termination: 2 ' 7 h q d e o h v z k h q u h j l v w h u h g + , * + d q g g l v d e o h v w h u p l q d w l r q u h v l v w d q f h l q w h u q d o w r w k h ' ' 5 6 ' 5 $ 0 : k h q h q d e o h g l q q r u p d o r s h u d w l r q 2 ' 7 l v r q o \ d s s o l h g w r h d f k r i w k h i r o o r z l q j v l j q d o v ' 4 > @ / ' 4 ; [ ? 8 ' 4 6 [ ? 8 ' 0 [ d q g / ' 0 [ 7 k h 2 ' 7 l q s x w l v l j q r u h g l i g l v d e o h g y l d w k h / 2 $ ' 0 2 ' ( u h j l v w h u f r p p d q g 2 ' 7 l v u h i h u h q f h g w r 9 u h i & $ reset: $ q l q s x w f r q w u r o s l q d f w l y h / 2 : u h i h u h q f h g w r 9 v v 7 k h 5 ( 6 ( 7 ? l q s x w u h f h l y h u l v d & 0 2 6 l q s x w g h i l q h g d v d u d l o w r u d l o v l j q d o z l w k ' & + , * + t [ 9 dd d q g ' & / 2 : d [ 9 dd q. 5 ( 6 ( 7 ? d v v h u w l r q d q g g h d v v h u w l r q d u h d v \ q f k u r q r x v data strobe, byte (per word): 2 x w s x w h g j h d o l j q h g z l w k 5 ( $ ' g d w d , q s x w f h q w h u d o l j q h g z l w k : 5 , 7 ( g d w d data input/output: / r z h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 data input/output: 8 s s h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 data input/output: / r z h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 data input/output: 8 s s h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 data input/output: / r z h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 data input/output: 8 s s h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 logic devices incorporated www.logicdevices.com 9 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 7 8 8 7 8 7 7 8 8 7 7 8 7 8 8 7 : < < : < : : < < : : < : < < : $ $ $ ' ' g2, g8, g13, j13, k5, k11, l2, l4, l6, l8, m2, 1 3 3 3 5 5 5 9 9 $ $ $ $ $ $ $ $ $ $ ' ' ' ' * * * g10, k3, k6, k9, k12, 5 5 5 5 9 9 9 9 $ $ $ $ $ $ $ $ $ $ ' ' ' g5, g11, k2, k8, k13, / / / 0 1 3 p4, p6, p8, r5, r11, 7 9 9 9 $ $ $ $ $ $ $ $ ' ' ' ' * * * * . . . . 5 5 5 5 9 9 9 9 $ $ $ $ $ $ $ $ t able 2 - b all /s ignal l ocation and d escription c ontinued ball assignments symbol type description dq 48, dq 49, dq 50, dq 51, dq 52, dq 53, dq 54, q 55 dq 56, dq 57, dq 58, dq 59, dq 60, dq 61, dq 62, dq 63 dq 64, dq 65, dq 66, dq 67, dq 68, dq 69, dq 70, dq 71 dq 72, dq 73, dq 74, dq 75, dq 76, dq 77, dq 78, dq 79 v dd v dd q v ss v ss q i/o i/o i/o i/o supply supply supply supply data input/output: / r z h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 data input/output: 8 s s h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 data input/output: / r z h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 data input/output: 8 s s h u % \ w h : 2 5 ' 3 l q u h i h u h q f h g w r 9 u h i ' 4 3 r z h u 6 x s s o \ 9 ? 9 ' d w d , 2 6 x s s o \ 9 ? 9 ground ' d w d , 2 * u r x q g , v r o d w h g i u r p & r u h i r u l p s u r y h g q r l v h l p p x q l w \ logic devices incorporated www.logicdevices.com 10 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product l3 n3 % % & & ( ( ) ) + + j1, l1, m1, n1, p1, p3, 8 8 : : < < t able 2 - b all /s ignal l ocation and d escription c ontinued ball assignments symbol type description v refca v refdq unpopulated supply supply 9 r o w d j h 5 h i h u h q f h & 2 5 ( 9 u h i & $ p x v w e h p d l q w d l q h g d w d o o w l p h v 9 r o w d j h 5 h i h u h q f h , 2 9 u h i ' 4 p x v w e h p d l q w d l q h g d w d o o w l p h v 8 q s r s x o d w h g x q s o d w h g p d w u l [ o r f d w l r q v 1.00 nom 1.00 nom 12.00 nom ? 1 r w h $ o o g l p h q v l r q v l q p p 0 $ ; 20.00 nom ? [ 1 2 0 $ b & d ( f g + j k l m n p r t 8 9 : < $ $ ? ? logic devices incorporated www.logicdevices.com 11 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 5 - m echanical d rawing p ackage o utline d imensions logic devices incorporated www.logicdevices.com 12 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 1 2 7 ( 6 9 dd d q g 9 dd 4 p x v w e h z l w k l q p 9 r i h d f k r w k h u d w d o o w l p h v d q g 9 5 ( ) p x v w q r w e h j u h d w h u w k d q [ 9 dd 4 : k h q 9 dd and 9 dd 4 d u h o h v v w k d q 0 9 9 5 ( ) p d \ e h d p 9 0 d [ r s h u d w l q j d p e l h q w w h p s h u d w x u h t $ l v p h d v x u h g l q w k h f h q w h u r i w k h s d f n d j h ' h y l f h ) x q f w l r q d o l w \ l v q r w j x d u d q w h h g l i w k h ' 5 $ 0 g h y l f h h [ f h h g v w k h 0 d [ l p x p 7 $ during operation. 1 2 7 ( 6 9 dd 9 ? p 9 9 dd q 9 dd 9 5 ( ) 9 ss i 0 + ] t $ = 25 & 9 2 8 7 ' & [ 9 dd q 9 2 8 7 s h d n w r s h d n 9 ' 0 l q s x w l v j u r x s h g z l w k , 2 s l q v u h i o h f w l q j w k h v l j q d o l v j u r x s h g z l w k ' 4 d q g w k h u h i r u h p d w f k h g l q o r d g l q j & & & 4 6 l v i r u ' 4 6 y v ' 4 6 ? & dio & , 2 ' 4 [ & , 2 > ' 4 6 @ & , 2 > ' 4 6 ? @ ( [ f o x g h v & . & . ? & ' , b & 1 7 / & , & 1 7 / [ & & . > & . @ & & . > & . ? @ & 1 7 / 2 ' 7 & 6 ? d q g & . ( & ' , b & 0 ' b $ ' ' 5 & , & 0 ' b $ ' ' 5 [ & & . > & . @ & & . > & . ? @ & 0 ' 5 $ 6 ? & $ 6 ? d q g : ( ? $ ' ' 5 > q @ capacitance parameter symbol min max min max min max units notes & . d q g & . ? single-end i/o: dq, dm ' l i i h u h q w l d o , 2 ' 4 6 ' 4 6 ? inputs 5 $ 6 ? & $ 6 ? : ( ? & 6 ? & . ( 5 ( 6 ( 7 ? $ ' ' 5 % $ t able 4: i nput /o utput c apacitance & & . & 10 & 10 & i_shared 3.0 1.5 1.5 4.0 6.1 2.5 2.5 pf pf pf pf 2 3 5 symbol parameter min max units notes 9 dd 9 dd q 9 in 9 2 8 7 t $ industrial t $ ( [ w h q g h g t $ 0 l o w h p s t stg 9 9 9 & & & & 1 1 1 2,3 2,3 2,3 2,3 t able 3: a bsolute m aximum r atings 85 105 125 120 -0.4 -0.4 -0.4 -40 -40 -55 -55 9 dd 6 x s s o \ 9 r o w d j h u h o d w l y h w r 9 ss 9 dd 6 x s s o \ 9 r o w d j h u h o d w l y h w r 9 ss q 9 r o w d j h r q d q \ s l q u h o d w l y h w r 9 ss 2 s h u d w l q j $ p e l h q w 7 h p s h u d w x u h 2 s h u d w l q j $ p e l h q w 7 h p s h u d w x u h 2 s h u d w l q j $ p e l h q w & d v h 7 h p s h u d w x u h 6 w r u d j h 7 h p s h u d w x u h 3.0 1.5 1.5 4.0 6.1 2.5 2.5 ddr3-1333 ddr3-1600 ddr3-1866 3.0 1.5 1.5 4.0 6.1 2.5 2.5 logic devices incorporated www.logicdevices.com 13 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t & . 0 , 1 , dd & / , dd t 5 & ' 0 , 1 , dd w 5 & 0 , 1 , dd t 5 $ 6 0 , 1 , dd t 5 3 0 , 1 , dd t ) $ : t rrd i dd t 5 ) & i dd parameter 10-10-10 11-11-11 13-13-13 t able 5: t iming p arameters for i dd m easurements - c lock u nits ns & . & . & . & . & . & . & . & . 1.5 10 10 34 24 10 30 5 ddr3-1333 -15 x64 x64 0 [ ; ddr3-1600 -12 ddr3-1866 -11 1.25 11 11 36 28 12 33 6 90 13 13 40 32 14 36 6 110 ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 00110000000 10000000000 10000000000 11110000000 11110000000 00100000000 001100000f0 100000000f0 100000000f0 111100000f0 111100000f0 001000000f0 1 2 3 4 5 6 7 repeat sub-loop 0, use ba [2:0] = 6 repeat sub-loop 0, use ba [2:0] = 7 - - - - - - - - repeat cycles n rc +1 through n rc +4 until 2 x rc - 1, truncate if needed repeat sub-loop 0, use ba [2:0] = 1 repeat sub-loop 0, use ba [2:0] = 2 repeat sub-loop 0, use ba [2:0] = 3 repeat sub-loop 0, use ba [2:0] = 4 repeat sub-loop 0, use ba [2:0] = 5 d\ d\ pre repeat cycles 1 through 4 until n ras - 1, truncate if needed repeat cycles 1 through 4 until n rc - 1, truncate if needed repeat cycles n rc +1 through n rc +4 until n rc - 1 + n ras - 1, truncate if needed - - - - d\ d\ pre act d d 4 x n rc 6 x n rc 8 x n rc 10 x n rc 12 x n rc 14 x n rc n rc + 3 n rc + 4 - n rc + n ras - 2 x nrc - n ras - n rc n rc + 1 n rc + 2 cycle number command 0 data 1 2 act d d 3 4 0 static high toggling logic devices incorporated www.logicdevices.com 14 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 6: i dd 0 m easurement l oop ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 00110000000 10000000000 10000000000 11110000000 11110000000 01010000000 00100000000 001100000f0 100000000f0 100000000f0 111100000f0 111100000f0 010100000f0 001000000f0 1 2 3 4 5 6 7 cycle number command data 0 1 2 act d d - 3 4 - nrcd - nras - nrc n rc +1 nrc +2 n rc +3 n rc +4 - n rc + nrcd - n rc + nras 2 x n rc 2 x n rc 2 x n rc 2 x n rc 2 x n rc 2 x n rc 2 x n rc d\ d\ rd pre act d d d\ d\ rd pre repeat sub-loop 0, use ba [2:0] = 1 - 00110011 - repeat sub-loop 0, use ba [2:0] = 2 repeat sub-loop 0, use ba [2:0] = 3 repeat sub-loop 0, use ba [2:0] = 4 repeat sub-loop 0, use ba [2:0] = 5 repeat sub-loop 0, use ba [2:0] = 6 repeat sub-loop 0, use ba [2:0] = 7 repeat cycles 1 through 4 until nrcd - 1, truncate if needed repeat cycles 1 through 4 until nras - 1, truncate if needed repeat cycles 1 through 4 until nrc - 1, truncate if needed repeat cycles nrc + 1 through nrc + 4 until nrc + nrcd - 1, truncate if needed repeat cycles nrc + 1 through nrc + 4 until nrc + nras - 1, truncate if needed - - - - - - - - 00000000 - toggling static high 0 repeat cycle nrc + 1 through nrc + 4 until 2 x nrc - 1, truncate if needed logic devices incorporated www.logicdevices.com 15 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 7: i dd 1 m easurement l oop logic devices incorporated www.logicdevices.com 16 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 8: i dd m easurement c onditions f or p ower -d own c urrents name 7 l p l q j 3 d w w h u q & . ( ( [ w h u q d o & o r f n t & . t 5 & t 5 $ 6 t 5 & ' t rrd t 5 & & / $ / & 6 ? & r p p d q g , q s x w v 5 2 : & 2 / 8 0 1 $ g g u % d q n $ g g u h v v dm data i/o 2 x w s x w % x i i h u ' 4 ' 4 6 odt burst length $ & 7 , 9 ( % d q n v , ' / ( % d q n v 6 s h f l d o 1 r w h v n/a / 2 : toggling t & . 0 , 1 , dd q ? d q ? d q ? d q ? d q ? d q ? d q ? d + , * + / 2 : / 2 : / 2 : / 2 : mid-level ( q d e o h g ( q d e o h g 2 ) ) 8 none $ o o q ? d n/a / 2 : toggling t & . 0 , 1 , dd q ? d q ? d q ? d q ? d q ? d q ? d q ? d + , * + / 2 : / 2 : / 2 : / 2 : mid-level ( q d e o h g ( q d e o h g 2 ) ) 8 none $ o o q ? d n/a + , * + toggling t & . 0 , 1 , dd q ? d q ? d q ? d q ? d q ? d q ? d q ? d + , * + / 2 : / 2 : / 2 : / 2 : mid-level ( q d e o h g ( q d e o h g 2 ) ) 8 none $ o o q ? d n/a / 2 : toggling t & . 0 , 1 , dd q ? d q ? d q ? d q ? d q ? d q ? d q ? d + , * + / 2 : / 2 : / 2 : / 2 : mid-level ( q d e o h g ( q d e o h g 2 ) ) 8 none $ o o q ? d i dd 2p0 precharge power- down current (slow exit) i dd 2p1 precharge power- down current (fast exit) i dd 2q precharge quiet standby current i dd 3p active power- down current ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 10000000000 10000000000 111100000f0 111100000f0 1 2 3 4 5 6 7 cycle number command data 0 1 0d d 2d \ 3d \ repeat sub-loop 0, use ba [2:0] = 7 - - - - 4-7 8-11 repeat sub-loop 0, use ba [2:0] = 1 repeat sub-loop 0, use ba [2:0] = 2 repeat sub-loop 0, use ba [2:0] = 3 repeat sub-loop 0, use ba [2:0] = 4 repeat sub-loop 0, use ba [2:0] = 5 repeat sub-loop 0, use ba [2:0] = 6 static high toggling 12-15 16-19 20-23 24-27 28-31 logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 9: i dd 2 n / i dd 3 n m easurement l oop ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 10000000000 10000000000 111100000f0 111100000f0 1 2 3 4 5 6 7 cycle number command data toggling static high 0 0 3 12-15 28-31 d - 1d - 2d \ - d\ - 4-7 repeat sub-loop 0, use ba [2:0] = 1; odt = 0 8-11 repeat sub-loop 0, use ba [2:0] = 2; odt = 1 repeat sub-loop 0, use ba [2:0] = 3; odt = 1 16-19 repeat sub-loop 0, use ba [2:0] = 4; odt = 0 20-23 repeat sub-loop 0, use ba [2:0] = 5; odt = 0 24-27 repeat sub-loop 0, use ba [2:0] = 6; odt = 1 repeat sub-loop 0, use ba [2:0] = 7; odt = 1 logic devices incorporated www.logicdevices.com 18 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 10: i dd 2 nt m easurement l oop ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 01010000000 10000000000 11110000000 11110000000 010100000f0 100000000f0 111100000f0 111100000f0 1 2 3 4 5 6 7 data 0 static high toggling 56-63 0 1 2 5 8-15 cycle number command rd d d\ d\ rd 3 4 - d d\ d\ 6 7 32-39 16-23 24-31 40-47 48-55 00000000 - - - 00110011 repeat sub-loop 0, use ba [2:0] = 7 - - repeat sub-loop 0, use ba [2:0] = 1 repeat sub-loop 0, use ba [2:0] = 2 repeat sub-loop 0, use ba [2:0] = 3 repeat sub-loop 0, use ba [2:0] = 4 repeat sub-loop 0, use ba [2:0] = 5 repeat sub-loop 0, use ba [2:0] = 6 logic devices incorporated www.logicdevices.com 19 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 11: i dd 4 r m easurement l oop ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 01001000000 10001000000 11111000000 11111000000 010010000f0 100010000f0 111110000f0 111110000f0 1 2 3 4 5 6 7 data 1d - wr toggling stac high 0 0 3 6 2d \ - 00000000 cycle number command d\ - 4wr 00110011 5d - d\ - 7d\ - 8-15 repeat sub-loop 0, use ba [2:0] = 1 16-23 repeat sub-loop 0, use ba [2:0] = 2 24-31 repeat sub-loop 0, use ba [2:0] = 3 32-39 repeat sub-loop 0, use ba [2:0] = 4 40-47 repeat sub-loop 0, use ba [2:0] = 5 48-55 repeat sub-loop 0, use ba [2:0] = 6 56-63 repeat sub-loop 0, use ba [2:0] = 7 logic devices incorporated www.logicdevices.com 20 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 12: i dd 4 w m easurement l oop ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 0 1b 1c 1d 1e 1f 1g 1h 2 9-12 13-16 cycle number command data 1 0 17-20 21-24 25-28 29-32 33-n rfc-1 repeat sub-loop 1a, use ba [2:0] = 1 repeat sub-loop 1a, use ba [2:0] = 2 1a 2 3 4 5-8 static high toggling ref d d d\ d\ repeat sub-loop 1a, use ba [2:0] = 4 repeat sub-loop 1a, use ba [2:0] = 5 repeat sub-loop 1a, use ba [2:0] = 6 repeat sub-loop 1a, use ba [2:0] = 3 repeat sub-loop 1a, use ba [2:0] = 7 repeat sub-loop 1a through 1h until n rfc - 1, truncate if needed logic devices incorporated www.logicdevices.com 21 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 13: i dd 5 b m easurement l oop p ackage o utline d imensions logic devices incorporated www.logicdevices.com 22 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 14: i dd m easurement l oop i dd test i dd 8: reset i dd 6e/m: self refresh current i dd 6: self refresh current ( [ w h q g h g r u 0 l o 7 h p s h u d w x u h 5 d q j h t $ ? & w r ? & r u ? & w r ? & industrial range t $ ? & w r ? & & . ( ( [ w h u q d o & o r f n t & . t 5 & t 5 $ 6 t 5 & ' t rrd t 5 & & / $ / & 6 ? & r p p d q g , q s x w v 5 2 : & 2 / 0 8 1 d g g u h v v h v % $ 1 . d g g u h v v h v data i/o 2 x w s x w e x i i h u ' 4 ' 4 6 odt burst length $ f w l y h % $ 1 . 6 , ' / ( % $ 1 . 6 srt $ 6 5 / 2 : 2 i i & . d q g & . ? / 2 : q ? d q ? d q ? d q ? d q ? d q ? d q ? d q ? d mid-level mid-level mid-level mid-level mid-level ( q d e o h g ( q d e o h g 0 l g o h y h o q ? d q ? d q ? d ' l v d e o h g q r u p d o ' l v d e o h g / 2 : 2 i i & . d q g & . ? / 2 : q ? d q ? d q ? d q ? d q ? d q ? d q ? d q ? d mid-level mid-level mid-level mid-level mid-level ( q d e o h g ( q d e o h g 0 l g o h y h o q ? d q ? d q ? d ( q d e o h g h [ w h q g h g ' l v d e o h g mid-level mid-level q ? d q ? d q ? d q ? d q ? d q ? d q ? d q ? d mid-level mid-level mid-level mid-level mid-level mid-level mid-level q ? d none $ o o q ? d q ? d ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 00110000000 01010001000 10000000000 001101000f0 010101010f0 100001000f0 2 3 100003000f0 5 6 7 8 100007000f0 001100000f0 010100010f0 100000000f0 00110100000 01010101000 10000100000 12 13 10000300000 15 16 17 18 10000700000 cycle number command data 1 0 2 - 00000000 - 3 n rrd n rrd + 1 n rrd + 2 n rrd + 3 2 x n rrd 3x n rrd 4 x n rrd 4 x n rrd + 1 n faw n faw + n rrd n faw + 2x n rrd n faw + 3x n rrd n faw + 4x n rrd n faw + 4x n rrd+1 2 x n faw 2 x n faw + 1 2 x n faw + 2 3 x nfaw + nrrd 3 x nfaw + 2x nrrd 2 x n faw + 3 2 x n faw + n rrd 2 x n faw + n rrd+1 2 x n faw + n rrd+2 2 x n faw + n rrd+3 2 x nfaw + 2x n rrd 1 4 9 10 11 14 static high toggling act rda d act 3 x nfaw + 3x nrrd 3 x nfaw + 4x nrrd 3 x nfaw + 4x nrrd +1 0 d act rda - repeat cycle 2 x n faw + 2 until 2 x n faw + n rrd - 1 19 2 x n faw + 3x n rrd 2 x n faw + 4x n rrd 2 x n faw+4x n rrd+1 3 x nfaw repeat sub-loop 11, use ba[2:0] = 3 - - - repeat sub-loop 1, use ba[2:0] = 5 repeat sub-loop 0, use ba[2:0] = 6 repeat sub-loop 1, use ba[2:0] = 7 repeat cycle n faw + 4 x n rrd until 2 x n faw - 1, if needed rda d - d repeat cycle 2 until n rrd - 1 repeat cycle n rrd + 2 until 2 x n rrd - 1 repeat sub-loop 0, use ba[2:0] = 2 repeat sub-loop 0, use ba[2:0] = 3 repeat cycle 4 x n rrd until n faw - 1, if needed 00110011 repeat sub-loop 10, use ba[2:0] = 2 - - rda d - 00110011 repeat sub-loop 0, use ba[2:0] = 4 d act d repeat cycle 2 x n faw + n rrd + 2 until 2 x n faw + 2 x n rrd - 1 00000000 - repeat cycle 3 x n faw + 4 x n rrd until 4 x n faw - 1, if needed repeat cycle 2 x n faw + 4 x n rrd until 3 x n faw - 1, if neede d repeat sub-loop 10, use ba[2:0] = 4 repeat sub-loop 11, use ba[2:0] = 5 repeat sub-loop 10, use ba[2:0] = 6 repeat sub-loop 11, use ba[2:0] = 7 d logic devices incorporated www.logicdevices.com 23 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 15: i dd 7 m easurement l oop 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 5 6 1 1 logic devices incorporated www.logicdevices.com 24 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 1 2 7 ( 6 1. t $ = 0 & w r d 85 & 6 5 7 d q g $ 6 5 d u h g l v d e o h g h q d e o l q j $ 6 5 f r x o g l q f u h d v h , dd [ e \ x s w r d q d g g l w l r q d o p $ 5 r r p w h p s h u d w x u h v h o i u h i u h v k o & w h p s h u d w x u h v h o i u h i u h v k ( o h y d w h g w h p s h u d w x u h v h o i u h i u h v k 7 f o & 6 5 7 l v g l v d e o h g $ 6 5 l v h q d e o h g 9 d o x h l v w \ s l f d o ( o h y d w h g w h p s h u d w x u h v h o i u h i u h v k o & 7 f o & 6 5 7 l v g l v d e o h g $ 6 5 l v h q d e o h g 9 d o x h l v p d [ l p x p ( [ w h q g h g w h p s h u d w x u h v h o i u h i u h v k 7 f o & 6 5 7 l v g l v d e o h g $ 6 5 l v h q d e o h g 9 d o x h l v w \ s l f d o ( [ w h q g h g w h p s h u d w x u h v h o i u h i u h v k o & 7 f ? o & 6 5 7 l v g l v d e o h g $ 6 5 l v h q d e o h g 9 d o x h l v p d [ l p x p i dd ddr3-1333 ddr3-1600 ddr3-1866 units notes i dd 0 i dd 1 i dd 2p0 i dd 2p1 i dd 2q i dd 2n i dd 2nt i dd 3p i dd 3n i dd 4r i dd : i dd 5b i dd 6 i dd 6 $ i dd 6 i dd ( 7 i dd i dd 8 speed bin p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ t able 16a: i dd m aximum l imits v dd =1.35v 290 420 60 130 120 120 150 200 965 18.5 35 42.5 90 1065 i dd 3 p $ 330 435 60 150 135 130 185 165 215 1135 815 18.5 35 42.5 90 1195 i dd 3 p $ 345 455 60 150 145 200 180 230 1220 930 18.5 35 42.5 90 1330 i dd 3 p $ 1 1 1 1 1 1 1 1 1 1 1 1 2 6 1 1 i dd ddr3-1333 ddr3-1600 ddr3-1866 units notes i dd 0 i dd 1 i dd 2p0 i dd 2p1 i dd 2q i dd 2n i dd 2nt i dd 3p i dd 3n i dd 4r i dd : i dd 5b i dd 6 i dd ( 7 i dd i dd 8 speed bin p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ t able 16b: i dd m aximum l imits v dd =1.5v 400 550 100 160 220 225 250 290 365 1200 1000 1050 110 110 140 1300 i dd 3 p $ 450 100 185 235 250 315 385 1400 1125 1100 110 110 140 1450 i dd 3 p $ 500 600 100 210 260 300 340 410 1500 1250 1150 110 110 140 1800 i dd 3 p $ p ackage o utline d imensions p ackage o utline d imensions logic devices incorporated www.logicdevices.com 25 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 1 2 7 ( 6 1. 9 dd d q g 9 dd 4 p x v w w u d f n r q h d q r w k h u 9 dd 4 p x v w e h o h v v w k d q r u h t x d o w r 9 dd 9 v v 9 v v 4 2. 9 dd d q g 9 dd 4 p d \ l q f o x g h $ & q r l v h r i ? p 9 n + ] w r 0 + ] l q d g g l w l r q w r w k h ' & + ] w r n + ] v s h f l i l f d w l r q v 9 dd d q g 9 dd 4 p x v w e h d w w k h v d p h o h y h o i r u y d o l g $ & w l p l q j s d u d p h w h u v 3. 9 5 ( ) v h h 7 d e o h 4. 7 k h p l q l p x p o l p l w u h t x l u h p h q w l v i r u w h v w l q j s x u s r v h v 7 k h o h d n d j h f x u u h q w r q w k h 9 5 ( ) s l q v k r x o g e h p l q l p d o parameter/condition symbol min typ max units notes supply voltage i/o supply voltage input leakage current: $ q \ l q s x w 9 d 9 in d 9 dd 9 5 ( ) s l q 9 d 9 in d 9 $ o o r w k h u s l q v q r w x q g h u w h v w 9 vref supply leakage current: 9 5 ( ) ' 4 9 dd r u 9 5 ( ) & $ 9 dd /2 $ o o r w k h u s l q v q r w x q g h u w h v w 9 9 9 ? $ ? $ 1,2 1,2 3,4 t able 17a: dc e lectrical c haracteristics and o perating c onditions v dd =1.35v 1.45 1.45 2 1 1.35 1.35 - - 1.3 1.3 -2 -1 $ o o 9 r o w d j h v d u h u h i h u h q f h g w r 9 v v 9 dd 9 dd q i i i 9 5 ( ) parameter/condition symbol min typ max units notes vin low; dc/commands/address busses vin high; dc/commands/address busses input reference voltage command/address bus i/o reference voltage dq bus i/o reference voltage dq bus in self refresh command/address termination voltage v \ v w h p o h y h o q r w g l u h f w ' 5 $ 0 l q s x w 9 9 9 9 9 9 1,2 2,3 4 5 t able 18: dc e lectrical c haracteristics and i nput c onditions 6 h h 7 d e o h 9 dd [ 9 dd [ 9 dd 9 dd - n/a n/a [ 9 dd [ 9 dd [ 9 dd [ 9 dd q 9 ss 6 h h 7 d e o h [ 9 dd [ 9 dd 9 ss - $ o o 9 r o w d j h v d u h u h i h u h q f h g w r 9 v v 9 il 9 , + 9 5 ( ) & $ ' & 9 5 ( ) ' 4 ' & 9 5 ( ) ' 4 6 5 9 tt p ackage o utline d imensions parameter/condition symbol min typ max units notes supply voltage i/o supply voltage input leakage current: $ q \ l q s x w 9 d 9 in d 9 dd 9 5 ( ) s l q 9 d 9 in d 9 $ o o r w k h u s l q v q r w x q g h u w h v w 9 vref supply leakage current: 9 5 ( ) ' 4 9 dd r u 9 5 ( ) & $ 9 dd /2 $ o o r w k h u s l q v q r w x q g h u w h v w 9 9 9 ? $ ? $ 1,2 1,2 3,4 t able 17b: dc e lectrical c haracteristics and o perating c onditions v dd =1.5v 2 1 1.5 1.5 - - 1.425 1.425 -2 -1 $ o o 9 r o w d j h v d u h u h i h u h q f h g w r 9 v v 9 dd 9 dd q i i i 9 5 ( ) 6 h h 1 2 7 ( 6 r q q h [ w s d j h p ackage o utline d imensions logic devices incorporated www.logicdevices.com 26 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product input high ac voltage: logic 1 input high ac voltage: logic 1 input high dc voltage: logic 1 input high dc voltage: logic 0 input high ac voltage: logic 0 input high ac voltage: logic 0 input high ac voltage: logic 1 input high ac voltage: logic 1 input high dc voltage: logic 1 input high dc voltage: logic 0 input high ac voltage: logic 0 input high ac voltage: logic 0 -100 -150 - -100 -150 - 9 , + $ & 0 , 1 9 , + $ & 0 , 1 9 , + ' & 0 , 1 9 , / ' & 0 $ ; 9 , / $ & 0 $ ; 9 , / $ & 0 $ ; 9 , + $ & 0 , 1 9 , + $ & 0 , 1 9 , + ' & 0 , 1 9 , / ' & 0 $ ; 9 , / $ & 0 $ ; 9 , / $ & 0 $ ; 1 2 7 ( 6 1. $ o o y r o w d j h v d u h u h i h u h q f h g w r 9 5 ( ) 9 5 ( ) l v 9 5 ( ) & $ i r u f r q w u r o f r p - p d q g d q g d g g u h v v $ o o v o h z u d w h v d q g v h w x s k r o g w l p h v d u h v s h f l i l h g d w w k h ' 5 $ 0 e d o o 9 5 ( ) l v 9 5 ( ) ' 4 i r u ' 4 d q g ' 0 l q s x w v 2. , q s x w v h w x s w l p l q j s d u d p h w h u v t is and t ' 6 d u h u h i h u h q f h g d w 9 il $ & 9 , + $ & q r w 9 5 ( ) ' & 3. , q s x w k r o g w l p l q j s d u d p h w h u v t , + d q g t ' + d u h u h i h u h q f h g d w 9 il ' & 9 , + ' & q r w 9 5 ( ) $ & 4. 6 l q j o h h q g h g l q s x w v o h z u d w h 9 q v p d [ l p x p l q s x w y r o w d j h v z l q j x q g h u w h v w l v p 9 s h d n w r s h d n parameter/condition symbol ddr3-1866 units & r p p d q g d q g $ g g u h v v t able 19: i nput s witching c onditions dq and dm ddr3-1600 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 ddr3-1333 1 2 7 ( 6 1. 9 5 ( ) & $ ' & l v h [ s h f w h g w r e h d s s u r [ l p d w h o \ [ 9 dd d q g w r w u d f n y d u l - d w l r q v l q w k h ' & o h y h o ( [ w h u q d o o \ j h q h u d w h g s h d n q r l v h q r q f r p p r q p r g h r q 9 5 ( ) & $ p d \ q r w h [ f h h g ? [ 9 dd d u r x q g w k h 9 5 ( ) & $ ' & y d o x h 3 h d n w r s h d n $ & q r l v h r q 9 5 ( ) & $ v k r x o g q r w h [ f h h g ? r i 9 5 ( ) & $ ' & 2. ' & y d o x h v d u h g h w h u p l q h g w r e h o h v v w k d q 0 + ] l q i u h t x h q f \ ' 5 $ 0 p x v w p h h w v s h f l i l f d w l r q v l i w k h ' 5 $ 0 l q g x f h v d g g l w l r q d o $ & q r l v h j u h d w h u w k d q 0 + ] l q i u h t x h q f \ 3. 9 5 ( ) ' 4 ' & l v h [ s h f w h g w r e h d s s u r [ l p d w h o \ [ 9 dd d q g w r w u d f n y d u l d w l r q v l q w k h ' & o h y h o ( [ w h u q d o o \ j h q h u d w h g s h d n q r l v h q r q f r p - p r q p r g h r q 9 5 ( ) ' 4 p d \ q r w h [ f h h g ? [ 9 dd around the 9 5 ( ) ' 4 ' & y d o x h 3 h d n w r s h d n $ & q r l v h r q 9 5 ( ) ' 4 v k r x o g q r w h [ f h h g ? r i 9 5 ( ) ' 4 ' & 4. 9 5 ( ) ' 4 ' & p d \ w u d q v l w l r q w r 9 5 ( ) ' 4 6 5 d q g e d f n w r 9 5 ( ) ' 4 ' & z k h q l q 6 ( / ) ] 5 ( ) 5 ( 6 + z l w k l q u h v w u l f w l r q v r x w o l q h g l q w k h 6 ( / ) 5 ( ) 5 ( 6 + v h f w l r q 5. 9 tt l v q r w d s s o l h g g l u h f w o \ w r w k h g h y l f h 9 tt l v d v \ v w h p v x s s o \ i r u v l j q d o w h u p l q d w l r q u h v l v w r u v 0 , 1 d q g 0 $ ; y d o x h v d u h v \ v w h p g h s h q - notes: 1. numbers in diagrams reflect nominal values. minimum v il and v ih levels 0.850v 0.775v 0.705v 0.690v 0.675v 0.660v 0.645v 0.575v 0.500v v ih (ac) v ih (dc) v il (dc) v il (ac) v il and v ih levels with ringback 1.90v 1.35v 0.850v 0.775v 0.705v 0.690v 0.675v 0.660v 0.645v 0.575v 0.500v 0.0v -0.40v v dd q + 0.4v narrow pulse width v dd q v ih (ac) v ih (dc) v ref + ac noise v ref + dc error v ref + dc error v ref + ac noise v il (dq) v il (ac) vss vss 0.4v narrow pulse width logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product operating conditions f igure 6 - i nput s ignal f igure 7 & 8: o vershoot /u ndershoot s pecifications maximum amplitude overshoot area v dd /v dd q time (ns) volts (v) maximum amplitude undershoot area time (ns) v ss /v ss q volts (v) figure 7: overshoot figure 8: undershoot ac overshoot/undershoot specification logic devices incorporated www.logicdevices.com 28 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product p ackage o utline d imensions p ackage o utline d imensions parameter ddr3-1333 ddr3-1600 ddr3-1866 maximum peak amplitude allowed for overshoot area v h h ) l j x u h maximum peak amplitude allowed for underrshoot area v h h ) l j x u h maximum overshoot area above v dd v h h ) l j x u h maximum undershoot area below vss v h h ) l j x u h t able 20: c ontrol and a ddress p ins 9 9 9 q v 9 q v parameter ddr3-1333 ddr3-1600 ddr3-1866 maximum peak amplitude allowed for overshoot area v h h ) l j x u h maximum peak amplitude allowed for undershoot area v h h ) l j x u h maximum overshoot area above v dd / v dd q v h h ) l j x u h maximum undershoot area below vss/ vssq v h h ) l j x u h t able 21: c lock , d ata , s trobe , and m ask p ins 9 9 9 q v 9 q v 9 9 9 q v 9 q v 9 9 9 q v 9 q v 9 9 9 q v 9 q v 9 9 9 q v 9 q v p ackage o utline d imensions logic devices incorporated www.logicdevices.com 29 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product parameter/condition symbol min max units notes differential input voltage, logic high - slew differential input voltage, logic low - slew differential input voltage, logic high differential input voltage, logic low differential input crossing voltage relative to v dd /2 for dqs, dqs\, ck, ck\ differential input crossing voltage relative to v dd /2 for ck, ck\ single-ended high level for strobes single-ended high level for ck, ck\ single-ended low level for strobes single-ended low level for ck, ck\ p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 4 4 5 6 5 6 t able 22: d ifferential i nput o perating c onditions (ck x , ck x \, dqs x , and dqs x \) n/a -200 9 dd 9 dd q [ 9 5 ( ) 9 il $ & 9 5 ( ) ' & 9 5 ( ) ' & 9 dd q 9 dd 9 dd 4 9 il $ & 9 dd /2 - 9 il $ & n/a [ 9 , + $ & 9 5 ( ) 9 ss 9 ss q 9 5 ( ) ' & 9 5 ( ) ' & 9 dd 4 9 , + $ & 9 dd 9 , + $ & 9 ss q 9 ss 9 , + ' , ) ) $ & v o h z 9 il ' , ) ) $ & v o h z 9 , + ' , ) ) $ & 9 il ' , ) ) $ & 9 , ; 9 , ; 9 6 + ( 9 6 ( / 1 2 7 ( 6 1. & o r f n l v u h i h u h q f h g w r 9 dd ' d q g 9 v v ' d w d v w u r e h l v u h i h u h q f h g w r 9 dd 4 d q g 9 v v 4 2. 5 h i h u h q f h l v 9 5 ( ) & $ ' & i r u f o r f n d q g i r u 9 5 ( ) ' 4 ' & i r u v w u r e h 3. ' l i i h u h q w l d o l q s x w v o h z u d w h 9 p v 4. ' h i l q h v v o h z u d w h u h i h u h q f h s r l q w v u h o d w l y h w r l q s x w f u r v v l q j y r o w d j h v 5. 0 $ ; o l p l w l v u h o d w l y h w r v l q j o h h q g h g v l j q d o v w k h r y h u v k r r w v s h f l i l f d - w l r q v d u h d s s o l f d e o h 6. 0 , 1 o l p l w l v u h o d w l y h w r v l q j o h h q g h g v l j q d o v w k h x q g h u v k r r w v s h f l i l f d - w l r q v d u h d s s o l f d e o h 7 k h w \ s l f d o y d o x h r i 9 , ; $ & l v h [ s h f w h g w r e h d e r x w [ 9 dd r i w k h w u d q v p l w w l q j g h y l f h d q g 9 , ; $ & l v h [ s h f w h g w r w u d f n y d u l d w l r q v l q 9 dd . 9 , ; $ & l q g l f d w h v w k h y r o w d j h d w z k l f k g l i i h u h q w l d o l q s x w v l j q d o v p x v w f u r v v 8. 7 k h 9 , ; h [ w h q g h g u d q j h ? p 9 l v d o o r z h g r q o \ i r u w k h f o r f n d q g w k l v 9 , ; h [ w h q g h g u d q j h l v r q o \ d o o r z h g z k h q w k h i r o o r z l q j f r q g l w l r q v d u h p h w 7 k h v l q j o h h q g h g l q s x w v l j q d o v d u h p r q r w r q l f k d y h w k h v l q j o h h q g h g v z l q j 9 6 ( / 9 6 ( + r i d w o h d v w 9 dd ? p 9 d q g w k h g l i i h u h q w l d o v o h z u d w h r i & . & . ? l v j u h d w h u w k d q 9 q v logic devices incorporated www.logicdevices.com 30 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product overshoot/undershoot specifications f igure 9 - v ix for d ifferential s ignals v ix x x x x v dd , v dd q v dd , v dd q ck#, dqs# ck#, dqs# v ix v ix v ix ck, dqs ck, dqs v ss , v ss q v ss , v ss q v dd /2, v dd q/2 v dd /2, v dd q/2 f igure 10 - s ingle -e nded r equirements for d ifferential s ignals v ss or v ss q v dd or v dd q v sel (max) v seh (min) v seh v sel v dd /2 or v dd q/2 ck or dqs logic devices incorporated www.logicdevices.com 31 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product overshoot/undershoot specifications f igure 11 - d efinition of d ifferential ac-s wing and t dvac v ihdiff ( ac ) min v ihdiff ( dc ) min 0.0 v ildiff ( dc ) max v ildiff (max) t dvac v ihdiff (min) v ildiff ( ac ) max half cycle t dvac ck - ck# dq s - dqs # p ackage o utline d imensions slew rate (v/ns) 350mv 300mv -4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0 <1.0 t able 23: d ifferential i nput o perating c onditions ( t dvac) for ck x , ck x \, dqs x , and dqs x \ 163 162 161 159 155 150 150 50 38 34 29 22 13 0 0 % h o r z 9 il $ & t dvac (ps) at [v ihdiff (ac) to v ildiff (ac)] p ackage o utline d imensions input edge from to calculation setup hold t able 24: s ingle -e nded i nput s lew r ate input slew rate (linear signals) rising falling rising falling measured 9 5 ( ) 9 5 ( ) 9 il ' & 0 d [ 9 , + ' & 0 , 1 9 , + $ & 0 , 1 9 il $ & 0 $ ; 9 5 ( ) 9 5 ( ) 9 , + $ & 0 , 1 9 5 ( ) 9 5 ( ) 9 il $ & 0 $ ; 'tfs 9 5 ( ) 9 il ' & 0 $ ; ' 7 ) + 9 , + ' & 0 , 1 9 5 ( ) ' 7 5 6 + logic devices incorporated www.logicdevices.com 32 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product slew rate definitions for single-ended input signals 6 h w x s t is and t ' 6 q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 5 ( ) d q g w k h i l u v w f u r v v l q j 9 , + $ & 0 , 1 6 h w x s t is and t ' 6 q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 5 ( ) d q w k h i l u v w f u r v v l q j r i 9 il $ & 0 $ ; + r o g t , + d q g t ' + q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 il ' & 0 $ ; d q g w k h i l u v w f u r v v l q j r i 9 5 ( ) . + r o g t , + d q g t ' + q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 , + ' & 0 , 1 d q g w k h i l u v w f u r v v l q j r i 9 5 ( ) . logic devices incorporated www.logicdevices.com 33 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product slew rate definitions for single-ended input signals f igure 12 - n ominal s lew r ate d efinition for s ingle -e nded i nput s ignals trs tfs trh tfh v ref dq or v ref ca v ih ( ac ) min v ih ( dc ) min v il ( ac ) max v il ( dc ) max v ref dq or v ref ca v ih ( ac ) min v ih ( dc ) min v il ( ac ) max v il ( dc ) max setup hold single-ended input voltage (dq, cmd, addr) single-ended input voltage (dq, cmd, addr) p ackage o utline d imensions input edge from to calculation ck and dqs reference t able 25: d ifferential i nput s lew r ate d efinition input slew rate (linear signals) rising falling measured 9 5 ( ) 9 5 ( ) 9 , + $ & 0 , 1 9 , / $ & 0 $ ; 9 , + ' , ) ) 0 , 1 - 9 il ' , ) ) 0 $ ; ' 7 5 ' , ) ) 9 , + ' , ) ) 0 , 1 9 il ' , ) ) 0 $ ; ' 7 ) ' , ) ) logic devices incorporated www.logicdevices.com 34 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product slew rate definitions for differential input signals , q s x w v o h z u d w h i r u g l i i h u h q w l d o v l j q d o v & . [ & . [ ? 8 ' 4 6 [ 8 ' 4 6 [ ? / ' 4 6 [ d q g / ' 4 6 [ ? d u h g h i l q h g d q g p h d v x u h g d v v k r z q l q 7 d e o h 7 k h q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q 9 il ' , ) ) 0 $ ; d q g 9 , + ' , ) ) 0 , 1 7 k h q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q 9 , + ' , ) ) 0 , 1 d q g 9 il ' , ) ) 0 $ ; f igure 13 - n ominal d ifferential i nput s lew r ate d efinition for dqs, dqs# and ck, ck# tr diff tf diff v ih ( diff ) min v il ( diff ) max 0 differential input voltage (dqs, dqs#; ck, ck#) logic devices incorporated www.logicdevices.com 35 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product odt characteristics r tt pu r tt pd odt chip in termination mode v dd q dq v ss q i out = i pd - i pu i pu i pd i out v out to other circuitry such as rcv, . . . 2 ' 7 u v h i i h f w l y h u h v l v w d q f h 5 tt l v g h i l q h g e \ 0 5 > d q g @ 2 ' 7 l v d s s o l h g w r w k h ' 4 [ 8 ' 0 [ / ' 0 [ 8 ' 4 6 [ 8 ' 4 6 [ ? / ' 4 6 [ d q g / ' 4 6 [ ? e d o o v 7 k h 2 ' 7 w d u j h w y d o x h v d u h o l v w h g l q 7 d e o h parameter/condition symbol min typ max units n o t e s r tt h i i h f w l y h l p s h g d q f h ' h y l d w l r q r i 9 0 z l w k u h v s h f w w r 9 dd q/2 % 1, 2, 4 1, 2, 3, 4 t able 26: o n -d ie t ermination dc e lectrical c haracteristics 5 r tt b ( ) ) ' 9 0 -5 6 h h 7 d e o h 1 2 7 ( 6 1. 7 r o h u d q f h o l p l w v d u h d s s o l f d e o h d i w h u d s u r s h u = 4 f d o l e u d w l r q k d v e h h q s h u i r u p h g d w d v w d e o h w h p s h u d w x u h d q g y r o w d j h 9 dd 4 9 dd 9 v v 4 9 v v 5 h i h u w r v 2 ' 7 6 h q v l w l y l w \ w r q s d j h l i h l w k h u w k h w h p s h u d w x u h r u y r o w d j h f k d q j h v d i w h u f d o l e u d w l r q 2. 0 h d v x u h p h q w g h i l q l w l r q i r u 5 tt $ s s o \ 9 , + $ & w r d s l q x q g h u w h v w d q g p h d v x u h w k h f x u u h q w , > 9 , + $ & @ w k h q d s s o \ 9 il $ & w r s l q x q g h u w h v w d q g p h d v x u h f x u u h q w , > 9 il $ & @ 9 il $ & 9 il $ & , > 9 , + $ & , 9 il $ & @ 3. 0 h d v x u h y r o w d j h 9 0 d w w k h w h v w h g s l q z l w k q r o r d g 4. ) r u h [ w h q g h g 0 , / w h p s g h y l f h v w k h p l q l p x p y d o x h v d u h g h u d w h g e \ z k h q w k h g h y l f h l v e h w z h h q ? & d q g ? & t $ r tt = [ 9 0 9 dd q ' 9 0 -1 x 100 f igure 14 - odt l evels and i-v c haracteristics p ackage o utline d imensions logic devices incorporated www.logicdevices.com 36 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product mr1 [ 9 , 6 , 2 ] 0, 1, 0 0, 0, 1 0, 1, 1 1, 0, 1 1, 0, 0 t able 27: rtt e ffective i mpedances [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q 9 il $ & w r 9 , + $ & [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q 9 il $ & w r 9 , + $ & [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q 9 il $ & w r 9 , + $ & [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q 9 il $ & w r 9 , + $ & [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q [ 9 dd q 9 il $ & w r 9 , + $ & r tt resistor vout min typ max units 120 : 60 : 40 : 30 : 20 : 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 r tt 120 pd 240 r tt 120 3 8 240 r tt 60 pd 120 r tt 60 3 8 240 r tt 40 pd 80 r tt 40 3 8 80 r tt 30 pd 60 r tt 30 3 8 60 r tt 20 pd 40 r tt 20 3 8 40 120 : 60 : 40 : 30 : 20 : logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product odt sensitivity , i h l w k h u w k h w h p s h u d w x u h r u y r o w d j h f k d q j h v d i w h u , 2 f d o l e u d w l r q w k h w r o h u d q f h o l p l w v o l v w h g l q 7 d e o h f d q e h h [ s h f w h g w r z l g h q d f f r u g l q j w r 7 d e o h v d q g symbol min max units r tt 5 = 4 t able 28: odt s ensitivity d efinition g 5 tt g 7 [ > ' 7 @ g 5 tt g 9 [ > ' 9 @ 0.9 - dr tt dt x dr tt g 9 [ > ' 9 @ t able 29 - odt t emperature & v oltage s ensitivity change min max units dr tt dt dr tt dv 0 0 1.5 0.15 0 0 2 ' 7 o r d g l q j g l i i h u v i u r p w k d w x v h g l q $ & w l p l q j p h d v x u h p h q w v 7 z r s d u d p - h w h u v g h i l q h z k h q 2 ' 7 w x u q v r q r u r i i v \ q f k u r q r x v o \ w z r g h i l q h z k h q 2 ' 7 w x u q v r q r u r i i $ v \ q f k u r q r x v o \ d q g d q r w k h u g h i l q h v z k h q 2 ' 7 w x u q v r q r u r i i g \ q d p l f d o o \ 7 d e o h r x w o l q h v d q g s u r y l g h v g h i l q l w l r q d q g p h d v x u h p h q w u h i h u h q f h v h w w l q j v i r u h d f k s d u d p h w h u 2 ' 7 w x u q r q w l p h e h j l q v z k h q w k h r x w s x w o h d y h v + , * + = d q g 2 ' 7 u h v l v - w d q f h e h j l q v w r w x u q r q 2 ' 7 w x u q r i i w l p h e h j l q v z k h q w k h r x w s x w o h d y h v / 2 : = d q g 2 ' 7 u h v l v w d q f h e h j l q v w r w x u q r i i odt timing definitions timing reference point dq, dm dqs, dqs# dut v ref v tt = v ss q v dd q/2 zq rzq = 240 v ss q r tt = 25 ck, ck# all rzqs are embedded in module f igure 15 - odt t iming r eference l oad ck ck # t aon v ss q dq, dm dqs, dqs# begin point: rising edge of ck - ck# defined by the end point of odtl on v sw 1 end point: extrapolated point at v ss q t sw 1 t sw 2 ck ck # v dd q/2 t aof end point: extrapolated point at v rtt _ nom v rtt _ nom v ss q t aon t aof v sw 2 v sw 2 v sw 1 t sw 1 t sw 1 begin point: rising edge of ck - ck# defined by the end point of odtl off logic devices incorporated www.logicdevices.com 38 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product p ackage o utline d imensions symbol begin point definition end point definition figure t aon t aof t aon pd t aof pd t adc t able 30: odt t iming d efinitions figure 25 on page 59 figure 25 on page 59 figure 26 on page 60 figure 26 on page 60 ) l j x u h r q s d j h ( [ w u d s r o d w h g s r l q w d w 9 v v 4 ( [ w u d s r o d w h g s r l q w d w 9 5 tt _norm ( [ w u d s r o d w h g s r l q w d w 9 v v 4 ( [ w u d s r o d w h g s r l q w d w 9 5 tt _nom ( [ w u d s r o d w h g s r l q w v d w 9 5 tt b : 5 d q g 9 5 tt _nom 5 l v l q j h g j h r i & . & . ? g h i l q h g e \ w k h h q g s r l q w r i 2 ' 7 / r q 5 l v l q j h g j h r i & . & . ? g h i l q h g e \ w k h h q g s r l q w r i 2 ' 7 / r i i 5 l v l q j h g j h r i & . & . ? z l w k 2 ' 7 i l u v w e h l q j u h j l v w h u h g + , * + 5 l v l q j h g j h r i & . & . ? z l w k 2 ' 7 i l u v w e h l q j u h j l v w h u h g / 2 : 5 l v l q j h g j h r i & . & . ? g h i l q h g e \ w k h h q g s r l q w r i 2 ' 7 / & 1 : 2 ' 7 / & : 1 r u 2 ' 7 / & : 1 p ackage o utline d imensions parameter r tt _norm setting r tt _wr_setting vsw1 vsw2 t aon t aof t aon pd t aof pd t adc t able 31: r eference s ettings for odt t iming m easurements p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 p 9 n/a n/a n/a n/a n/a n/a n/a n/a 5 = 4 : 5 = 4 : 5 = 4 : 5 = 4 : 5 = 4 : 5 = 4 : 5 = 4 : 5 = 4 : 5 = 4 : 5 = 4 : measured f igure 16 - t aon and t aof d efinitions odt timing definitions ck ck # t aonpd v ss q dq, dm dqs, dqs# begin point: rising edge of ck - ck# with odt first registered high v sw 1 end point: extrapolated point at v ss q t sw 2 ck ck # v dd q/2 t aofpd end point: extrapolated point at v rtt _ nom v rtt _ nom v ss q t aonpd t aofpd t sw 1 t sw 2 t sw 1 v sw 2 v sw 2 v sw 1 begin point: rising edge of ck - ck# with odt first registered low logic devices incorporated www.logicdevices.com 39 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product odt characteristics f igure 17 - t aonpd and t aofpd d efinition f igure 18 - t adc d efinition ck ck # t adc dq, dm dqs, dqs# end point: extrapolated point at v rtt _ nom t sw 21 t adc end point: extrapolated point at v rtt _ wr v dd q/2 v ss q v rtt _ nom v rtt _ wr v rtt _ nom t sw 11 v sw 1 v sw 2 t sw 12 t sw 22 begin point: rising edge of ck - ck# defined by the end point of odtl cnw begin point: rising edge of ck - ck# defined by the end point of odtl cnw 4 or odtl cnw 8 r on pu r on pd output driver to other circuitry such as rcv, . . . chip in drive mode v dd q v ss q i pu i pd i out v out dq logic devices incorporated www.logicdevices.com 40 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product output driver impedance f igure 19 - o utput d river 34 o hm o utput d river i mpedance the 34 : g u l y h u 0 5 > @ l v w k h g h i d x o w g u l y h u 8 q o h v v r w k h u z l v h v w d w h g d o o w l p l q j v d q g v s h f l i l f d w l r q v o l v w h g k h u h l q d s s o \ w r w k h : driver only. its l p s h g d q f h 5 on l v g h i l q h g e \ w k h y d o x h r i w k h h [ w h u q d o u h i h u h q f h u h v l v w r u 5 = 4 d v i r o o r z v 5 on 5 = 4 z l w k q r p l q d o 5 = 4 : ? d q g l v d f w x - ally 34.3 : ? 7 k h : r x w s x w g u l y h u l p s h g d q f h f k d u d f w h u l v w l f v d u h o l v w h g l q 7 d e o h p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units notes 0, 1 t able 32: 34 : d river i mpedance c haracteristics 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 % 1 1 1 1 1 1 1, 2 9 dd q 9 dd q 9 dd q 9 dd q 9 dd q 9 dd q 9 dd q 34.3 : r on 34 pd r on 34 pu 0.6 0.9 0.9 0.9 0.9 0.6 -10 1.0 1.0 1.0 1.0 1.0 1.0 n/a 1.1 1.1 1.4 1.4 1.1 1.1 10 pull-up/pull-down mismatch (mm pupd ) 1 2 7 ( 6 1. 7 r o h u d q f h o l p l w v d v v x p h 5 = 4 r i : ? d q g d u h d s s o l f d e o h d i w h u s u r s h u = 4 f d o l e u d w l r q k d v e h h q s h u i r u p h g d w d v w d e o h w h p s h u d w x u h d q g y r o w d j h 9 dd 4 9 dd 9 v v 4 9 v v 5 h i h u w r v 2 k p g u l y h v h q v l w l y l w \ w l i h l w k h u w k h w h p s h u d w x u h r u w k h y r o w d j h f k d q j h v d i w h u f d o l e u d w l r q 2. 0 h d v x u h p h q w g h i l q l w l r q i r u p l v p d w f k e h w z h h q s x o o x s d q g s x o o g r z q 0 0 3 8 3 ' 0 h d u x u h e r w k 5 2 1 3 8 and r onpd d w [ 9 dd q: mm 3 8 ' = r on nom r 2 1 3 8 - r onpd logic devices incorporated www.logicdevices.com 41 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 34 o hm output driver impedance 34 o hm d river the 34 : g u l y h u u v f x u u h q w u d q j h k d v e h h q f d o f x o d w h g d q g v x p p d u l ] h g l q 7 d e o h i r u 9 dd 9 7 d e o h i r u 9 dd 9 d q g 7 d e o h i r u 9 dd 9 7 k h l q g l y l g x d o s x o o x s d q g s x o o g r z q u h v l v w r u v 5 2 1 3 ' d q g 5 2 1 3 8 d u h g h i l q h g d v i r o o r z v z l w k w k h , p s h g d q f h & d o f x o d w l r q v o l v w h g l q 7 d e o h x r on 3 ' 9 2 8 7 > , 2 8 7 @ 5 2 1 3 8 l v w x u q h g r i i x r on 3 8 9 dd 4 9 2 8 7 > , 2 8 7 @ 5 2 1 3 ' l v w x u q h g r i i p ackage o utline d imensions mr1[5,1] ron resistor vout min typ max units 0, 1 t able 33: 34 : d river p ull -u p and p ull -d own i mpedance c alculations : : : : : : 9 dd q 9 dd q 9 dd q 9 dd q 9 dd q 9 dd q 34.3 : r on 34 pd r on 34 pu 2.04 30.5 30.5 30.5 30.5 20.4 34.3 34.3 34.3 34.3 34.3 34.3 38.1 38.1 48.5 48.5 38.1 38.1 242.4 34.6 240 34.3 33.9 : : r on min typ max units rzq = 240 :1% rzq = (240 :1%)/7 p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units 0, 1 p $ p $ p $ p $ p $ p $ i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q 34.3 : r on 34 pd r on 34 pu 15.5 25.8 41.2 41.2 25.8 15.5 9.2 23 36.8 36.8 23 9.2 8.3 26 26 8.3 t able 35: 34 : d river i oh /i ol c haracteristics : v dd =v dd q=1.575v p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units 0, 1 p $ p $ p $ p $ p $ p $ i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q 34.3 : r on 34 pd r on 34 pu 24.6 39.3 39.3 24.6 8.8 21.9 35 35 21.9 8.8 24.8 24.8 t able 34: 34 : d river i oh /i ol c haracteristics : v dd = v dd q = 1.5v logic devices incorporated www.logicdevices.com 42 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 34 o hm output driver impedance p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units 0, 1 p $ p $ p $ p $ p $ p $ i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q i ol # [ 9 dd q 34.3 : r on 34 pd r on 34 pu 14 23.3 23.3 14 8.3 20.8 33.3 33.3 20.8 8.3 23.5 23.5 t able 36: 34 : d river i oh /i ol c haracteristics : v dd =v dd q=1.425v 34 : output driver sensitivity , i h l w k h u w k h w h p s h u d w x u h r u y r o w d j h f k d q j h v d i w h u = 4 f d o l e u d w l r q w k h w r o h u d q f h o l p l w v o l v w h g l q 7 d e o h f d q e h h [ s h f w h g w r z l g h q d f f r u g l q j w r 7 d e o h d q g symbol min max units r on @ 0.8 x v dd q r on @ 0.5 x v dd q r on @ 0.2 x v dd q 5 = 4 5 = 4 5 = 4 t able 37: 34 : o utput d river s ensitivity d efinition 1.1 - dr on g 7 + [ > ' 7 @ g 5 on g 9 + [ > ' 9 @ 1.1 - dr on dtm x [ ' 7 @ g 5 on g 9 0 [ > ' 9 @ 1.1 - dr on dtl x [ ' 7 @ g 5 on g 9 / [ > ' 9 @ 0.9 - dr on g 7 + [ > ' 7 @ g 5 on g 9 + [ > ' 9 @ 0.9 - dr on dtm x [ ' 7 @ g 5 on g 9 0 [ > ' 9 @ 0.9 - dr on dtl x [ ' 7 @ g 5 on g 9 / [ > ' 9 @ change min max units dr on dtm dr on dvm dr on dtl dr on dvl dr on dth dr on dvh ? & p 9 ? & p 9 ? & p 9 t able 38: 34 : o utput d river v oltage and t emperature s ensitivity 1.5 0.13 1.5 0.13 1.5 0.13 0 0 0 0 0 0 logic devices incorporated www.logicdevices.com 43 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product alternative 40 ohm driver p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units notes 0, 1 t able 39 - 40 : d river i mpedance c haracteristics 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 % 1 1 1 1 1 1 1, 2 9 dd q 9 dd q 9 dd q 9 dd q 9 dd q 9 dd q 9 dd q 40.0 : r on 40 pd r on 40 pu 0.6 0.9 0.9 0.9 0.9 0.6 -10 1.0 1.0 1.0 1.0 1.0 1.0 n/a 1.1 1.1 1.4 1.4 1.1 1.1 10 pull-up/pull-down mismatch (mm pupd ) 1 2 7 ( 6 1. 7 r o h u d q f h o l p l w v d v v x p h 5 = 4 r i : ? d q g d u h d s s o l f d e o h d i w h u s u r s h u = 4 f d o l e u d w l r q k d v e h h q s h u i r u p h g d w d v w d e o h w h p s h u d w x u h d q g y r o w d j h 9 dd 4 9 dd 9 v v 4 9 v v 5 h i h u w r v 2 k p g u l y h v h q v l w l y l w \ w l i h l w k h u w k h w h p s h u d w x u h r u w k h y r o w d j h f k d q j h v d i w h u f d o l e u d w l r q 2. 0 h d v x u h p h q w g h i l q l w l r q i r u p l v p d w f k e h w z h h q s x o o x s d q g s x o o g r z q 0 0 3 8 3 ' 0 h d u x u h e r w k 5 on 3 8 d q g 5 on 3 ' d w [ 9 dd q: mm 3 8 3 ' = r on nom r 2 1 3 8 - r onpd x 100 40 : output driver sensitivity , i h l w k h u w k h w h p s h u d w x u h r u y r o w d j h f k d q j h v d i w h u , 2 f d o l e u d w l r q w k h w r o h u d q f h o l p l w v o l v w h g l q 7 d e o h f d q e h h [ s h f w h g w r z l g h q d f f r u g l q j w r 7 d e o h d q g symbol min max units r on @ 0.8 x v dd q r on @ 0.5 x v dd q r on @ 0.2 x v dd q 5 = 4 5 = 4 5 = 4 t able 40: 40 : o utput d river s ensitivity d efinition 1.1 - dr on g 7 + [ > ' 7 @ g 5 on g 9 + [ > ' 9 @ 1.1 - dr on dtm x [ ' 7 @ g 5 on g 9 0 [ > ' 9 @ 1.1 - dr on dtl x [ ' 7 @ g 5 on g 9 / [ > ' 9 @ 0.9 - dr on g 7 + [ > ' 7 @ g 5 on g 9 + [ > ' 9 @ 0.9 - dr on dtm x [ ' 7 @ g 5 on g 9 0 [ > ' 9 @ 0.9 - dr on dtl x [ ' 7 @ g 5 on g 9 / [ > ' 9 @ logic devices incorporated www.logicdevices.com 44 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product alternative 40 ohm driver change min max units dr on dtm dr on dvm dr on dtl dr on dvl dr on dth dr on dvh ? & p 9 ? & p 9 ? & p 9 t able 41: 40 : o utput d river v oltage and t emperature s ensitivity 1.5 0.15 1.5 0.15 1.5 0.15 0 0 0 0 0 0 output characteristics and operating conditions 7 k h 6 ' 5 $ 0 x v h v e r w k v l q j o h h q g h g d q g g l i i h u h q w l d o r x w s x w g u l y h u v 7 k h v l q j o h h q g h g r x w s x w g u l y h u l v v x p p d u l ] h g l q 7 d e o h z k l o h w k h g l i i h u h q w l d o r x w s x w g u l y h u l v v x p p d u l ] h g l q 7 d e o h p ackage o utline d imensions parameter/condition symbol min max units notes output leakage current: ' 4 d u h g l v d e o h g 9 d 9 2 8 7 d 9 dd 4 2 ' 7 l v g l v d e o h g 2 ' 7 l v + , * + output slew rate: 6 l q j o h h q g h g i r u u l v l q j d q g i d o o l q j h g j h v p h d v x u h e h w z h h q 9 ol $ & 9 5 ( ) [ 9 dd q d q g 9 2 + $ & 9 5 ( ) [ 9 dd q single-ended dc high-level output voltage single-ended dc mid-point level output voltage single-ended dc low-point level output voltage single-ended dc high-point level output voltage single-ended dc low-point level output voltage delta r on between pull-up and pull-down for dq/dqs test load for ac timing and output slew rates x $ 9 q v 9 9 9 9 9 % 1 1, 2, 3, 4 1, 2, 5 1, 2, 5 1, 2, 5 1, 2, 3, 6 1, 2, 3, 6 3 t able 42: s ingle -e nded o utput d river characteristics 5 6 10 -5 2.5 -10 i 2 = 6 5 4 6 ( 9 2 + ' & 9 om ' & 9 ol ' & 9 2 + $ & 9 ol $ & mm 3 8 3 ' [ 9 dd q [ 9 dd q [ 9 dd q 9 7 7 [ 9 dd q 9 7 7 [ 9 dd q 2 x w s x w w r 9 tt 9 dd 4 y l d : resistor 5. 6 h h 7 d e o h r q s d j h , 9 f x u y h o l q h d u l w \ ' r q r w x v h $ & 7 h v w o r d g 6. 6 h h 7 d e o h r q s d j h i r u r x w s x w v o h z u d w h 6 h h 7 d e o h r q s d j h i r u d g g l w l r q d o l q i r u p d w l r q 8. 6 h h ) l j x u h r q s d j h i r u d q h [ d p s o h r i d v l q j o h h q g h g r x w s x w signal. 1 2 7 ( 6 1. 5 = 4 r i : ? z l w k 5 = 4 h q d e o h g g h i d x o w : g u l y h u d q g l v d s s o l - f d e o h d i w h u s u r s h u = 4 f d o l e u d w l r q k d v e h h q s h u i r u p h g d w d v w d e o h w h p - s h u d w x u h d q g y r o w d j h 9 dd 4 9 dd 9 v v 4 9 v v 2. 9 tt 9 dd q/2 3. 6 h h ) l j x u h r q s d j h i r u w k h w h v w o r d g f r q i l j x u d w l r q 4. 7 k h 9 q v p d [ l p x p l v d s s o l f d e o h i r u d v l q j o h ' 4 v l j q d o z k h q l w l v v z l w f k - l q j i u r p h l w k h u + , * + w r / 2 : r u / 2 : w r + , * + z k l o h w k h u h p d l q l q j ' 4 v l j q d o v l q w k h v d p h e \ w h o d q h d u h f r p e l q d w l r q v w k h p d [ l p x p o l p l w r i 9 q v p d [ l p x p l v u h g x f h g w r 9 q v logic devices incorporated www.logicdevices.com 45 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product p ackage o utline d imensions parameter/condition symbol min max units notes output leakage current: ' 4 d u h g l v d e o h g 9 d 9 2 8 7 d 9 dd 4 2 ' 7 l v + , * + output slew rate: ' l i i h u h q w l d o i r u u l v l q j d q g i d o o l q j h g j h v p h d v x u h e h w z h h q 9 ol ' , ) ) $ & [ 9 dd 4 d q g 9 2 + $ & [ 9 dd q output differential cross-point voltage differential high-level output voltage differential low-level output voltage delta r on between pull-up and pull-down for dq/dqs test load for ac timing and output slew rates x $ 9 q v p 9 9 9 % 1 1 1, 2, 3 1, 4 1, 4 1, 5 3 t able 43: d ifferential o utput d river characteristics 5 12 9 5 ( ) 10 -5 5 9 5 ( ) -150 -10 i 2 = srqdiff 9 2 ; $ & 9 2 + ' , ) ) $ & 9 ol ' , ) ) $ & mm 3 8 3 ' [ 9 dd q [ 9 dd q 2 x w s x w w r 9 tt 9 dd 4 y l d : resistor 4. 6 h h 7 d e o h r q s d j h i r u w k h r x w s x w v o h z u d w h 5. 6 h h 7 d e o h r q s d j h i r u d g g l w l r q d o l q i r u p d w l r q 6. 6 h h ) l j x u h r q s d j h i r u d q h [ d p s o h r i d g l i i h u h q w l d o r x w s x w v l j q d o 1 2 7 ( 6 1. 5 = 4 r i : ? z l w k 5 = 4 h q d e o h g g h i d x o w : g u l y h u d q g l v d s s o l - f d e o h d i w h u s u r s h u = 4 f d o l e u d w l r q k d v e h h q s h u i r u p h g d w d v w d e o h w h p - s h u d w x u h d q g y r o w d j h 9 dd 4 9 dd 9 v v 4 9 v v 2. 9 5 ( ) 9 dd q/2 3. 6 h h ) l j x u h r q s d j h i r u w k h w h v w o r d g f r q i l j x u d w l r q f igure 20 - dq o utput s ignal v oh ( ac ) min output max output v ol ( ac ) logic devices incorporated www.logicdevices.com 46 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 21 - d ifferential o utput s ignal v oh ( diff ) min output max output v ol ( diff ) v ox ( ac ) max v ox ( ac ) min x x x x output characteristics and operating conditions reference output load ) l j x u h u h s u h v h q w v w k h h i i h f w l y h u h i h u h q f h o r d g r i : x v h g l q g h i l q l q j w k h u h o h y d q w g h y l f h $ & w l p l q j s d u d p h w h u v h [ f h s w 2 ' 7 u h i h u h q f h w l p l q j d v z h o o d v w k h r x w s x w v o h z u d w h p h d v x u h p h q w v , w l v q r w l q w h q g h g w r e h d s u h f l v h u h s u h v h q w d w l r q r i d s d u w l f x o d u v \ v w h p h q y l u r q p h q w r u d g h s l f w l r q r i w k h d f w x d o o r d g s u h v h q w h g e \ d q \ v s h f l i l f , q g x v w u \ w h v w v \ v w h p d s s d u d w x v 6 \ v w h p g h v l j q h u v v k r x o g x v h , % , 6 r u r w k h u v l p x o d w l r q w r r o v w r f r u u h o d w h w k h w l p l q j u h i h u h q f h o r d g s u h v h q w h g r u h [ k l e l w h g r q w k h v \ v w h p r u v \ v w h p h q y l u r q p h q w f igure 22 - r eference o utput l oad for ac t iming and o utput s lew r ate timing reference point dq dqs dqs# dut v ref v tt = v dd q/2 v dd q/2 zq rzq = 240 v ss r tt = 25 all rzqs are embedded in module p ackage o utline d imensions output edge from to calculation dq t able 44: s ingle -e nded o utput s lew r ate output slew rate (linear signals) rising falling measured 9 ol $ & 9 2 + $ & 9 2 + $ & 9 ol $ & 9 2 + $ & 9 ol $ & ' 7 5 6 ( 9 2 + $ & 9 ol $ & ' 7 ) 6 ( logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product slew rate definitions for single-ended output signals 7 k h v l q j o h h q g h g r x w s x w g u l y h u l v v x p p d u l ] h g l q 7 d e o h : l w k w k h u h i h u h q f h o r d g i r u w l p l q j p h d v x u h p h q w v w k h r x w s x w v o h z u d w h i r u i d o o l q j d q g u l v l q j h g j h v l v g h i l q h g d q g p h d v x u h g e h w z h h q 9 ol $ & d q g 9 2 + $ & i r u v l q j o h h q g h g v l j q d o v d v l q g l f d w h g l q 7 d e o h d q g ) l j x u h f igure 23 - n ominal s lew r ate d efinition for s ingle -e nded o utput s ignals tr se tf se v oh ( ac ) v ol ( ac ) v tt p ackage o utline d imensions output edge from to calculation dqs, dqs\ t able 45: d ifferential o utput s lew r ate d efinition output slew rate (linear signals) rising falling measured 9 ol ' , ) ) $ & 9 2 + ' , ) ) $ & 9 2 + ' , ) ) $ & 9 ol ' , ) ) $ & 9 2 + ' , ) ) $ & 9 ol ' , ) ) $ & 'trdiff 9 2 + ' , ) ) $ & 9 ol ' , ) ) $ & 'tfdiff logic devices incorporated www.logicdevices.com 48 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product slew rate definitions for differential output signals 7 k h g l i i h u h q w l d o r x w s x w g u l y h u l v v x p p d u l ] h g l q 7 d e o h : l w k w k h u h i h u h q f h o r d g i r u w l p l q j p h d v x u h p h q w v w k h r x w s x w v o h z u d w h i r u i d o o l q j d q g u l v l q j h g j h v l v g h i l q h g d q g p h d v x u h g e h w z h h q 9 ol $ & d q g 9 2 + $ & i r u g l i i h u h q w l d o v l j q d o v d v v k r z q l q 7 d e o h d q g ) l j x u h f igure 24 - n ominal d ifferential o utput s lew r ate d efinition for dqs, dqs# tf diff v oh ( diff ) ac v ol ( diff ) ac 0 logic devices incorporated www.logicdevices.com 49 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product p ackage o utline d imensions parameter symbol min max min max min max units notes $ & 7 , 9 $ 7 ( w r l q w h u q d o 5 ( $ ' r u : 5 , 7 ( g h o d \ w l p h 3 5 ( & + $ 5 * ( f r p p d q g s h u l r g $ & 7 , 9 $ 7 ( w r $ & 7 , 9 $ 7 ( r u 5 ( ) 5 ( 6 + f r p p d q g s h u l r g $ & 7 , 9 $ 7 ( w r 3 5 ( & + $ 5 * ( f r p p d q g s h u l r g & / & / & / & / 6 x s s r u w h g & / 6 h w w l q j v 6 x s s r u w h g & : / 6 h w w l q j v 1 2 3 3 2 3 3 3 2,3 3 3 3 2,3 t able 46: s peed b ins ' ' 5 ' ' 5 ' ' 5 t 5 & ' t rp t 5 & t 5 $ 6 t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * t & . $ 9 * 5, 6, 8, 10 5, 6, 8, 10 5, 6, 8, 10 15 15 51 36 3 2.5 1.5 - - - p v 3.3 3.3 <2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns & . & . & : / & : / & : / & : / & : / & : / & : / & : / & : / & : / & : / & : / 3. 5 h v h u y h g i l o o h g e o r f n v v h w w l q j v d u h q r w d o o r z h g 1 2 7 ( 6 1. t 5 ( ) , g h s h q g v r q t 2 3 ( 5 2. 7 k h & / d q g & : / v h w w l q j u h v x o w l q t & . u h t x l u h p h q w v : k h q p d n l q j d v h o h f w l r q r i t & . e r w k & / d q g & : / u h t x l u h p h q w v h w w l q j v q h h g w r e h i x o - i l o o h g 15 15 51 36 3 2.5 1.5 - - - p v 3.3 3.3 <2 15 15 51 36 3 2.5 1.5 - - - p v 3.3 3.3 <2 > & : / @ > & : / @ > & : / @ logic devices incorporated www.logicdevices.com 50 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 47 ( sheet 1 of 6) - e lectrical c haracteristics and ac o perating conditions min max 8 8 8 0.47 0.47 -80 -70 7800 3900 2900 0.53 0.53 80 70 -118 -140 -155 -168 -177 -186 -193 -200 -205 -210 -215 118 140 155 168 177 186 193 200 205 210 215 units notes [cwl=1.5; 10-10-10] symbol parameter -15 (ddr3-1333) 11 cycles 12 cycles 0.43 - t errnper min = (1+0.68ln[n]) x t jitper min t errnper max = (1+0.68ln[n]) x t jitper max 9,42 9,42 9,42 10,11 12 12 13 13 16 16 17 17 17 17 17 17 17 17 17 17 17 14 15 17 140 160 t errnper t jitcc t jitcc, lck t err6perr t err7perr t err8perr n = 13, 14 49, 50 cycles t err2perr t err3perr t err4perr t err5perr t err9perr t err10perr t err11perr t err12perr cumulave error across 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles clock period jitter cycle-to-cycle jitter dll locked dll locking dll locked dll locking clock absolute period clock absolute high pusle width clock absolute low pulse width t clk (abs) t ckdll_dis t cl (avg) t ch (abs) t cl (abs) clock period average: dll enable mode high pulse width average low pulse width average clock period average: dll disable mode tc = 85?c to 105?c t jitper t jitper, lck t ck (avg) - 0.43 ns ck ck ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps t ck (avg) ps ns t ck (avg) min= t ck (avg) min+ t jitper min; max= t ck (avg)max+ t jitper max tc = 0?c to <85?c tc = >105?c to 125?c t ch (avg) see speed bin table (#49) for tck range allowed [cwl=1.25; 11-11-11] -12 (ddr3-1600) [cwl=1.07; 13-13-13] -11 (ddr3-1866) min max min max 8 8 8 0.47 0.47 -70 -60 7800 3900 2900 0.53 0.53 70 60 -103 -122 -136 -147 -155 -163 -169 -175 -180 -184 -188 103 122 136 147 155 163 169 175 180 184 188 0.43 - 120 140 - 0.43 8 8 8 0.47 0.47 -60 -50 7800 3900 2900 0.53 0.53 60 50 0.43 - - 0.43 100 120 -88 -105 -117 -126 -133 -139 -145 -150 -154 -158 -161 88 105 117 126 133 139 145 150 154 158 161 logic devices incorporated www.logicdevices.com 51 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 47 ( sheet 2 of 6) - e lectrical c haracteristics and ac o perating conditions min max - data setup me to dqs, dqs\ t ds ac150 data hold me from dqs, dqs\ vref @ 1v/ns data setup me to dqs, dqs\ t ds ac175 base (speci?caon) vref @ 1v/ns base (speci?caon) vref @ 1v/ns base (speci?caon) dq high-a me from ck, ck\ dqs, dqs\ differential read postamble t rpst dqs, dqs\ differential output high me dq low-z me from ck, ck\ dq strobe input timing dqs, dqs\ differential write postamble parameter -15 (ddr3-1333) [cwl=1.5; 10-10-10] symbol dqs, dqs\ falling setup to ck, ck\ rising t dss dq output timing dqs, dqs\ to dq skew, per access dq output hold me from dqs, dqs\ t dqss dqs, dqs\ differential input low pulse width t wpst dqs,dqs\ rising to ck, ck\ rising t dqsl dqs, dqs\ differential input high pulse width t dqsh dqs, dqs\ differential read preamble t rpre dqs, dqs\ falling hold from ck, ck\ rising t dsh dqs, dqs\ differential write preamble t wpre dq strobe output timing t qsh dqs, dqs\ differential output low me t qsl dqs, dqs\ rising to/from rising ck, ck\ t dqsck dqs, dqs\ high-z me (rl+bl/2) t hz (dqs) dqs, dqs\ low-z me (rl-1) t lz (dqs) dqs, dqs\ rising to/from rising ck, ck\ when dll is disabled t dqsk dll_dis t dh ac100 minimum data pulse width t dipw t qh t dqsq - - 30 180 65 165 400 - -500 -0.25 0.45 0.45 0.2 0.2 0.9 0.3 -255 0.4 0.4 -500 - 0.9 0.3 1 0.38 - - - - - - - 125 250 250 0.25 0.55 0.55 - - - - 255 - - 250 250 note 24 note 27 10 - units ps ps ps ps ps ps ps ps ps ps ck ck ck ck ck ck ck ps ck ck ps ps ck ck ns tck (avg) 18,19 19,20 18,19 19,20 18,19 19,20 41 22,23 22,23 25 25 25 23 21 21 22,23 22,23 23,24 23,27 notes 26 21 t hz (dq) t lz (dq) -12 (ddr3-1600) [cwl=1.25; 11-11-11] -11 (ddr3-1866) [cwl=1.07; 13-13-13] min max min max - - 10 160 45 145 360 - -450 - -0.27 0.45 0.45 0.18 0.18 0.9 0.3 -225 0.4 0.4 -450 - 0.9 0.3 1 0.38 - - - - - - - 100 225 225 0.27 0.55 0.55 - - - - 225 - - 225 225 note 24 note 27 10 - dq input timing 65 200 150 275 100 200 535 - -390 - 0.38 -0.27 0.45 0.45 0.18 0.18 0.9 0.3 -195 0.4 0.4 -390 - 0.9 0.3 1 - - - - - - - 85 190 190 - 0.27 0.55 0.55 - - - - 195 - - 195 195 note 24 note 27 10 logic devices incorporated www.logicdevices.com 52 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 47 ( sheet 3 of 6) - e lectrical c haracteristics and ac o perating conditions min max - - - - - - - - - - multipurpose register read burst end to mode register set for mulpurpose register exit t mprr min = 1ck; max = n/a min = 4ck; max = n/a min = greater of 12ck or 15ns; max = n/a mode register set command cycle me t mrd min = greater of 4ck or 7.5ns; max = n/a min = 4ck; max = n/a auto precharge write recovery + precharge me t dal min = wr + t rp/ t ck (avg); max = n/a cas\-to-cas\ command delay t ccd min = 15ns; max = n/a delay from start of internal write transacon to internal read command t wtr min = greater of 4ck or 7.5ns; max = n/a write recovery me t wr mode register set command update delay t mod four activate windows for 2kb page size four activate windows for 1kb page size t faw read-to-prechare me t rtp [cwl=1.5; 10-10-10] symbol parameter -15 (ddr3-1333) command and address timing ctrl, cmd, addr setup to ck, ck\ base (speci?caon) vref @ 1v/ns ctrl, cmd, addr setup to ck, ck\ base (speci?caon) vref @ 1v/ns ctrl, cmd, addr hold to ck, ck\ base (speci?caon) vref @ 1v/ns dll locking me t dllk see "speed bin table (#49) for trcd see "speed bin table (#49) for trp see "speed bin table (#49) for tras minimum ctrl, cmd, addr pulse width t ipw activate to internal read or write delay t rcd precharge command period t rp 1kb page size activate-to-precharge command period t ras activate-to-activate command period t rcd see "speed bin table (#49) for trc min=greater of 4ck or 6ns ck ps ps ps ps ps ps ps ns ns ns ns ns ns ck ck ck ck ck ck ck ck units ck ck 28 29,30 20,30 29,30 20,30 29,30 20,30 41 31 31 31,32 31 31 31 31,32,33 31,34 notes 31 31 activate-to-activate minimum command period 2kb page size t rrd min max [cwl=1.25; 11-11-11] -12 (ddr3-1600) min max [cwl=1.07; 13-13-13] -11 (ddr3-1866) min=greater of 4ck or 6ns min=greater of 4ck or 7.5ns - - - - - - - - - - 512 65 200 150 275 100 200 535 25 35 - - - - - - - - - - min=greater of 4ck or 5ns min=greater of 4ck or 6ns t is ac175 t is ac150 t ih dc100 30 45 512 65 240 190 340 140 240 620 30 40 512 45 220 170 320 120 220 560 logic devices incorporated www.logicdevices.com 53 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 47 ( sheet 4 of 6) - e lectrical c haracteristics and ac o perating conditions min max valid clocks aer self refresh entry or power-down entry t cksre min = greater of 5ck or 10ns; max = n/a valid clocks before self refresh exit, power-down exit, or reset exit t cksrx min = greater of 5ck or 10ns; max = n/a exit self refresh to commands requiring a locked dll t xsdll min = t dllk (min); max = n/a minimum cke low pulse width for self refresh entry to self refresh exit ming t ckesr min = t cke (min) + ck; max = n/a self refresh timing exit self refresh to commands not requiring a locked dll t xs min = greater of 5ck or t rfc + 10ns; max = n/a maximum refresh period/interval tc 85?c t refi 7.8 tc >85?c 105?c 3.9 tc >105?c 125?c 2.9 tc 85?c - tc >105?c 125?c 24 tc >85?c 105?c maximum refresh period begin power supply ramp to power supplies stable t vddpr min = n/a; max = 200 refresh-to-activate or refresh command period t rfc min = 110; max = 9 x t refi refresh timing reset\ low to power supplies stable t rps min = 0; max = 200 reset\ low to i/o and rtt high-z t ioz min = n/a; max = 200 zqcs command: short calibraon time t zqcs exit reset from cke high to a valid command t xpr min = greater of 5ck or trfc + 10ns; max = n/a inializaon and reset timing 256 64 512 - - - zqcl command: long calibraon me power-up and reset operaon normal operaon t zqinit t zqoper 35 36 36 36 36 36 36 28 notes [cwl=1.5; 10-10-10] symbol calibraon timing parameter -15 (ddr3-1333) ck ck ck ms ns ms ms ms s s s ck ck ck ck ck ms ns ck units min max [cwl=1.25; 11-11-11] -12 (ddr3-1600) min max [cwl=1.07; 13-13-13] -11 (ddr3-1866) 256 64 512 - - - 256 64 512 - - - 64 (1x) 32 (2x) logic devices incorporated www.logicdevices.com 54 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 47 ( sheet 5 of 6) - e lectrical c haracteristics and ac o perating conditions min max min = greater of 10ck or 24ns; max = n/a bl8 (otf, mrs) bc4otf t wrapden min = wl + 4 + wr + 1 min = wl + 2 + wr + 1 bl8 (otf, mrs) bc4otf t wrpden t wrpden min = wl + 4 + t wr/ t ck (avg) t wrapden bc4mrs min = wl + 2 + t wr/ t ck (avg) write with auto precharge command to power-down entry bc4mrs dll on, any valid command, or dll o? to commands not requiring dll locked t xp read/read with auto precharge commant to power-down entry t rdpden min = rl + 4 + 1 write command to power- down entry refresh command to power-down entry t refpden min = 1 mrs command to power-down entry t mrspden min = t mod (min) t actpden min = 1 precharge/precharge all command to power-down entry t prpden min = 1 command pass disable delay t cpded min = 1; max = n/a power-down entry to power-down exit ming t pd min = tcke (min); max = 60ms power-down entry period: odt eher synchronous or asynchronous pde greater of tanpd or trfc - refresh command to cke low me power-down exit period: odt either synchronous or asynchronous pdx t anpd + t xpdll greater of 3ck or 5.625ns begin power-down period prior to cke registered high t anpd wl - 1ck power-down timing power-down entry minimum timing power-down exit timing precharge power-down with dll o? to command requiring dll locked t xpdll cke min pulse width t cke (min) activate command to power-down entry parameter -15 (ddr3-1333) ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck units 37 28 notes [cwl=1.5; 10-10-10] symbol min max -12 (ddr3-1600) [cwl=1.25; 11-11-11] min max -11 (ddr3-1866) [cwl=1.07; 13-13-13] min = greater of 3ck or 6.0ns; max = n/a greater of 3ck or 5ns min = 2 min = 2 min = 2 greater of 3ck or 5ns logic devices incorporated www.logicdevices.com 55 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 47 ( sheet 6 of 6) - e lectrical c haracteristics and ac o perating conditions min max write leveling output error t wloe t wls t wlh write leveling output delay t wlo write leveling hold from rising dqs, dqs\ crossing to rising ck, ck\ crossing dqs; dqs\ delay t wldqsen write leveling setup from rising ck, ck\ crossing to rising dqs, dqs\ crossing -250 0.3 0.3 40 25 0 0 195 195 250 0.7 0.7 - - 9 2 - - 6ck + odtl off rtt dynamic change skew t adc first dqs, dqs\ rising edge t wlmrd rtt_nom-to=rtt_wr change skew odtl cnw wl - 2ck rtt_wr-to-rtt_nom change skew - bc4 odtl cnw4 4ck + odtl off rtt_wr-to-rtt_nom change skew - bc8 odtl cnw8 odt high me without write command or with write command and bc8 odt h8 min = 6; max = n/a odt high me without write command or with write command and bc4 odt h4 min = 4; max = n/a asynchronous rtt turn-off delay (power-down with dll off) t aofpd min = 2; max = 8.5 t aon rtt turn-off from odtl off reference t aof asynchronous rtt turn-on delay (power-down with dll off) t aonpd min = 2; max = 8.5 odt timing dynamic odt timing write leveling timing rtt synchronous turn-on delay odtl on rtt synchronous turn-off delay odtl o? rtt turn-on from odtl on reference parameter -15 (ddr3-1333) ck ck ps ck ck ck ck ck ck ck ns ns ps ps ck ck ns ns units 38 40 23,38 39,40 39 38 40 notes [cwl=1.5; 10-10-10] symbol min max -12 (ddr3-1600) [cwl=1.25; 11-11-11 ] min max -11 (ddr3-1866) [cwl=1.07; 13-13-13] -225 0.3 0.3 40 25 0 0 165 165 225 0.7 0.7 - - 7.5 2 - - -195 0.3 0.3 40 25 0 0 140 140 195 0.7 0.7 - - 7.5 2 - - logic devices incorporated www.logicdevices.com 56 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product n otes 1. 3 d u d p h w h u v d u h d s s o l f d e o h z l w k ? & d t $ d ? & d q g 9 dd 9 dd 4 9 ? 9 2. $ o o y r o w d j h v d u h u h i h u h q f h g w r 9 v v 3. 2 x w s x w w l p l q j v d u h r q o \ y d o l g i r u 5 on r x w s x w e x i i h u v h o h f w l r q 4. 8 q l w t & . $ 9 * u h s u h v h q w v w k h d f w x d o t & . $ 9 * r i w k h l q s x w f o r f n x q g h u r s h u d w l r q 8 q l w & . u h s u h v h q w v r q h f o r f n f \ f o h r i w k h l q s x w f o r f n f r x q w l q j w k h d f w x d o f o r f n h g j h v 5. $ & w l p l q j d q g , dd w h v w v p d \ x v h d 9 il w r 9 , + v z l q j r i x s w r p 9 , w k h w h v w h q y l u r q p h q w e x w l q s x w w l p l q j l v v w l o o u h i h u h q f h g w r 9 5 ( ) h [ f h s w t is, t , + t ds, and t ' + x v h w k h $ & ' & w u l s s r l q w v d q g & . & . ? d q g ' 4 6 ' 4 6 ? x v h w k h l u f u r v v l q j s r l q w v 7 k h p l q l p x p v o h z u d w h i r u w k h l q s x w v l j q d o v x v h g w r w h v w w k h g h y l f h l v 9 q v i r u v l q j o h h q g h g l q s x w v d q g 9 q v i r u g l i i h u h q w l d o l q s x w v l q w k h u d q j h e h w z h h q 9 il $ & d q g 9 , + $ & 6. $ o o w l p l q j v w k d w x v h w l p h e d v h g y d o x h v q v ? v p v v k r x o g x v h t & . $ 9 * w r g h w h u p l q h w k h f r u u h f w q x p e h u r i f o r f n v 7 d e o h x v h v & . r u & . $ 9 * l q w h u f k d q j h d e o \ , q w k h d p e l h q w r i q r q l q w h u j h u u h v x o w v d o o p l q l p x p o l p l w v d u h w r e h u r x q g h g x s w r w k h q h d u h v w z k r o h l q w h j h u 7 k h x v h r i 6 7 5 2 % ( r u ' 4 6 ' , ) ) u h i h u v w r w k h ' 4 6 d q g ' 4 6 ? g l i i h u h q- w l d o f u r v v l q j s r l q w z k h q ' 4 6 l v w k h u l v l q j h g j h 7 k h x v h r i & / 2 & . r u & . u h i h u v w r w k h & . d q g & . ? g l i i h u h q w l d o f u r v v l q j s r l q w z k h q & . l v w k h rising edge. 8. 7 k l v r x w s x w o r d g l v x v h g i r u d o o $ & w l p l q j h [ f h s w 2 ' 7 u h i h u h q f h w l p l q j d q g v o h z u d w h v 7 k h d f w x d o w h v w o r d g p d \ e h g l i i h u h q w 7 k h r x w s x w v l j q d o y r o w d j h u h i h u h q f h s r l q w l v 9 dd 4 i r u v l q j o h h q g h g v l j q d o v d q g w k h f u r v v l q j s r l q w i r u g l i i h u h q w l d o v l j q d o v 9. : k h q r s h u d w l q j l q ' / / g l v d e o h p r g h / 2 * , & ' h y l f h v , q f / ' , g r h v q r w z d u u d q w f r p s o l d q f h z l w k q r u p d o p r g h w l p l q j v r u i x q f w l r q d o l w \ 10. 7 k h f o r f n u v t & . $ 9 * l v w k h d y h u d j h f o r f n r y h u d q \ f r q v h f x w l y h f o r f n v d q g t & . $ 9 * 0 , 1 l v w k h v p d o o h v w f o r f n u d w h d o o r z h g z l w k w k h h [ f h s w l r q r i d g h y l d w l r q g x h w r f o r f n m l w w h u , q s x w f o r f n m l w w h u l v d o o r z h g s u r y l g h g l w g r h v q r w h [ f h h g y d o x h v v s h f l i l h g d q g p x v w e h r i d u d q g r p * d x v v l d q g l v w u l e x w l r q l q q d w x u h 11. 6 s u h d g v s h f w u x p l v q r w l q f o x g h g l q w k h m l w w h u v s h f l i l f d w l r q y d o x h v + r z - h y h u w k h l q s x w f o r f n f d q d f f r p p r g d w h v s u h d g v s h f w u x p d w d v z h h s u d w h l q w k h u d q j h r i n + ] z l w k d q g d g g l w l r q d o r i t & . $ 9 * d v d o r q j w h u p m l w w h u f r p s r q h q w k r z h y h u w k h v s u h d g v s h f w u x p p d \ q r w x v h d f o r f n u d w h e h o r z t & . $ 9 * 0 , 1 12. 7 k h f o r f n u v t & + $ 9 * d q g t & / $ 9 * d u h w k h d y h u d j h k d o i f o r f n s h u l r g r y h u d q \ f r q v h f x w l y h f o r f n v d q g l v w k h v p d o o h v w f o r f n k d o i s h u l r g d o o r z h g z l w k w k h h [ f h s w l r q r i y d o x h v v s h f l i l h g d q g p x v w r i d u d q g r p * d x v v l d q g l v w u l e x w l r q l q q d w x u h 13. 7 k h s h u l r g m l w w h u t - , 7 3 ( 5 l v w k h p d [ l p x p g h y l d w l r q l q w k h f o r f n s h u l r g i u r p w k h d y h u d j h r u q r p l q d o f o r f n , w l v d o o r z h g l q h l w k h u w k h s r v l w l y h r u q h j d w l y h g l u h f w l r q 14. t & + $ % 6 l v w k h d e v r o x w h l q v w d q w d q h r x v f o r f n k l j k s x o v h z l g w k d v p h d - v x u h g i u r p r q h u l v l q j h g j h w r w k h i r o o r z l q j i d o o l q j h g j h 15. t & / $ % 6 l v w k h d e v r o x w h l q v w d q w d q h r x v f o r f n o r z s x o v h z l g w k d v p h d- v x u h g i u r p r q h i d o o l q j h g j h w r w k h i r o o r z l q j u l v l q j h g j h 16. 7 k h f \ f o h w r f \ f o h m l w w h u t - , 7 & & l v w k h d p r x q w w k h f o r f n s h u l r g f d q g h y l d w h i u r p r q h f \ f o h w r w k h q h [ w , w l v l p s r u w d q w w r n h h s f \ f o h w r f \ f o h m l w w h u d w d p l q l p x p g x u l q j w k h ' / / o r f n l q j w l p h 7 k h f x p x o d w l y h m l w w h u h u u r u t ( 5 5 q 3 ( 5 z k h u h q l v w k h q x p e h u r i f o r f n v e h w z h h q d q g l v w k h d p r x q w r i f o r f n w l p h d o o r z h g w r d f f x - p x o d w h f r q v h f x w l y h o \ d z d \ i u r p w k h d y h u d j h f o r f n r y h u q q x p e h u r i f o r f n f \ f o h v 18. t ' 6 e d v h d q g t ' + e d v h y d o x h v d u h i r u d v l q j o h h q g h g 9 q v ' 4 v o h z u d w h d q g 9 q v i r u g l i i h u h q w l d o ' 4 6 ' 4 6 ? v o h z u d w h 19. 7 k h v h s d u d p h w h u v d u h p h d v x u h g i u r p d g d w d v l j q d o ' 0 ' 4 ' 4 h ' 4 q d q g v r i r u w k w u d q v l w l r q h g j h w r l w v u h v s h f w l y h g d w d v w u r e h v l j q d o ' 4 6 ' 4 6 ? f u r v v l q j 20. 7 k h v h w x s d q g k r o g w l p h v d u h o l v w h g f r q y h u w l q j w k h e d v h v s h f l i l f d w l r q y d o x h v w r z k l f k g h u d w l q j w d e o h v d s s o \ w r 9 5 ( ) z k h q w k h v o h z u d w h l v 9 q v 7 k h v h y d o x h v z l w k d v o h z u d w h r i 9 q v d u h i r u u h i h u h q f h r q o \ 21. : k h q w k h g h y l f h l v r s h u d w h g z l w k l q s x w f o r f n m l w w h u w k l v s d u d p h w h u q h h g v w r e h g h u d w h g e \ w k h d f w x d o t - , 7 3 ( 5 o d u j h u r i t - , 7 3 ( 5 0 , 1 r u t - , 7 3 ( 5 0 $ ; r i w k h l q s x w f o r f n r x w s x w g h u d w l q j v d u h u h o d w l y h w r w k h 6 ' 5 $ 0 l q s x w f o r f n 22. 6 l q j o h h q g h g v l j q d o s d u d p h w h u 23. 7 k h 6 ' 5 $ 0 r x w s x w w l p l q j l v d o l j q h g w r w k h q r p l q d o r u d y h u d j h f o r f n 0 r v w r x w s x w s d u d p h w h u v p x v w e h g h u d w h g e \ w k h d f w x d o m l w w h u h u u r u z k h q l q s x w f o r f n m l w w h u l v s u h v h q w h y h q z k h q z l w k l q v s h f l i l f d w l r q 7 k l v u h v x o w v l q h d f k s d u d p h w h u e h f r p l q j o d u j h u 7 k h i r o o r z l q j s d u d p h w h u v d u h u h t x l u h g w r e h g h u d w h g e \ v x e w u d f w l q j t ( 5 5 3 ( 5 0 $ ; t ' 4 6 & . 0 , 1 t / = ' 4 6 0 $ ; t / = ' 4 0 $ ; d q g t $ 2 1 0 $ ; 7 k h s d u d p h - ter t 5 3 5 ( 0 , 1 l v g h u d w h g e \ v x e w u d f w l q j t - , 7 3 ( 5 0 $ ; z k l o h t 5 3 5 ( 0 $ ; l v g h u d w h g e \ t - , 7 3 ( 5 0 , 1 24. 7 k h p d [ l p x p s u h d p e o h l v e r x q g e \ t / = ' 4 6 0 $ ; 25. 7 k h v h s d u d p h w h u v d u h p h d v x u h g i u r p d g d w d v w u r e h v l j q d o ' 4 6 ' 4 6 ? f u r v v l q j w r l w v u h v s h f w l y h f o r f n v l j q d o & . & . ? f u r v v l q j 7 k h v s h f l - i l f d w l r q y d o x h v d u h q r w d i i h f w h g e \ w k h d p r x q w r i f o r f n m l w w h u d s s o l h g d v w k h v h d u h u h o d w l y h w r w k h f o r f n v l j q d o f u r v v l q j 7 k h v h s d u d p h w h u v v k r x o g e h p h w z k h w k h u f o r f n m l w w h u l v s u h v h q w r u q r w 26. the t ' 4 6 & . ' / / b ' , 6 s d u d p h w h u e h j l q v & / $ / f \ f o h v d i w h u w k h 5 ( $ ' f r p p d q g 7 k h p d [ l p x p s r v w d p e o h l v e r x q g e \ t + = ' 4 6 0 $ ; 28. & r p p d q g v u h t x l u l q j d o r f n h g ' / / d u h 5 ( $ ' d q g 5 ' $ 3 d q g v \ q - f k u r q r x v 2 ' 7 f r p p d q g v , q d g g l w l r q d i w h u d q \ f k d q j h r i o d w h q f \ t ; 3 ' / / w l p l q j p x v w e h p h w 29. t , 6 e d v h d q g t , + e d v h y d o x h v d u h i r u d v l q j o h h q g h g 9 q v f r q w u r o f r p p d q g d g g u h v v v o h z u d w h d q g 9 q v & . & . g l i i h u h q w l d o v o h z u d w h 30. 7 k h v h s d u d p h w h u v d u h p h d v x u h g i u r p d f r p p d q g d g g u h v v v l j q d o w u d q- v l w l r q h g j h w r l w v u h v s h f w l y h f o r f n & . & . ? v l j q d o f u r v v l q j 7 k h v s h f l - i l f d w l r q y d o x h v d u h q r w d i i h f w h g e \ w k h d p r x q w r i f o r f n m l w w h u d s s o l h g d v w k h v h w x s d q g k r o g w l p h v d u h u h o d w l y h w r w k h f o r f n v l j q d o f u r v v l q j w k d w o d w f k h v w k h f r p p d q g d g g u h v v 7 k h v h s d u d p h w h u v v k r x o g e h p h w z k h w k h u f o r f n m l w w h u l v s u h v h q w r u q r w 7 , v q h h g v w r e h g h u d w h g e h g h u d w h g l q f u h d v h g e \ g x h w r d g g h g o r d g w r w k h g u l y h u v $ q d o w h u q d w l y h p h w k r g l v w r l q f u h d v h g u l y h u v w u h q j w k i r u & 7 5 / & 0 2 d q g $ ' ' 5 31. ) r u w k h v h s d u d p h w h u v w k h ' ' 5 6 ' 5 $ 0 g h y l f h v x s s r u w v w q 3 $ 5 $ 0 logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product n otes c ontinued q & . 5 8 t 3 $ 5 $ 0 > q v @ t & . > $ 9 * @ > q v @ d v v x p l q j d o o l q s x w f o r f n m l w w h u v s h f l i l f d w l r q v d u h v d w l v i l h g ) r u h [ d p s o h w k h g h y l f h z l o o v x s s r u w t q 5 3 q & . 5 8 t 5 3 t & . > $ 9 * @ l i d o o l q s x w f o r f n m l w w h u v s h f l i l f d w l r q v d u h p h w 7 k l v p h d q v i r u ' ' 5 r i z k l f k t rp = 15ns, the g h y l f h z l o o v x s s r u w t q 5 3 5 8 t rp/ t & . > $ 9 * @ d v o r q j d v w k h l q s x w f o r f n m l w w h u v s h f l i l f d w l r q v d u h p h w 7 k d w l v w k h 3 5 ( & + $ 5 * ( f r p p d q g d w 7 d q g w k h $ & 7 , 9 $ 7 ( f r p p d q g d w 7 d u h y d o l g h y h q l i v l [ f o r f n v d u h o h v v w k d q q v g x h w r l q s x w f o r f n m l w w h u 32. ' x u l q j 5 ( $ ' v d q g : 5 , 7 ( v z l w k $ 8 7 2 3 5 ( & + $ 5 * ( w k h ' ' 5 6 ' 5 $ 0 z l o o k r o g r i i w k h l q w h u q d o 3 5 ( & + $ 5 * ( f r p p d q g x q w l o t 5 $ 6 0 , 1 k d v e h h q v d w l v i l h g 33. : k h q r s h u d w l q j l q ' / / g l v d e o h p r g h w k h j u h d w h u r i & . r u q v l v v d w l v i l h g i r u t : 5 34. 7 k h v w d u w r i w k h z u l w h u h f r y h u \ w l p h l v g h i l q h g d v i r o o r z v x ) r u % / i l [ h g e \ 0 5 6 d q g 2 7 ) 5 l v l q j f o r f n h g j h i r x u f o r f n f \ f o h v d i w h u : / x ) r u % & 2 7 ) 5 l v l q j f o r f n h g j h i r x u f o r f n f \ f o h v d i w h u : / x ) r u % & i l [ h g e \ 0 5 6 5 l v l q j f o r f n h g j h w z r f o r f n f \ f o h v d i w h u : / 35. 5 ( 6 ( 7 ? v k r x o g e h / 2 : d v v r r q d v s r z h u v w d u w v w r u d p s w r h q v x u h w k h r x w s x w v d u h l q + , * + = 8 q w l o 5 ( 6 ( 7 ? l v / 2 : w k h r x w s x w v d u h d w u l v n r i g u l y l q j w k h e x v d q g f r x o g u h v x o w l q h [ f h v v l y h f x u u h q w g h s h q g l q j r q w k h e x v d f w l y l w \ 36. 7 k h u h i u h v k s h u l r g l v p v z k h q t $ l v o h v v w k d q r u h t x d o w r ? & 7 k l v h t x d w h v w r d q d y h u d j h u h i u h v k u d w h r i ? v + r z h y h u q l q h 5 ( ) 5 ( 6 + f r p p d q g v v k r x o g e h d v v h u w h g d w o h d v w r q f h h y h u \ ? v : k h q t $ l v j u h d w h u w k d q ? & w k h u h i u h v k s h u l r g l v p v d q g z k h q t $ l v j u h d w h u w k d q ? & w k h u h i u h v k s h u l r g l v p v $ o w k r x j k & . ( l v d o o r z h g w r e h u h j l v w h u h g / 2 : d i w h u d 5 ( ) 5 ( 6 + f r p p d q g z k h q t 5 ( ) 3 ' ( 1 0 , 1 l v v d w l v i l h g w k h u h d u h f d v h v z k h u h d g g l w l r q d o w l p h v x f k d v t ; 3 ' / / 0 , 1 l v u h t x l u h g 38. 2 ' 7 w x u q r q w l p h 0 , 1 l v z k h q w k h g h y l f h o h d y h v + , * + = d q g 2 ' 7 u h v l v w d q f h e h j l q v w r w x u q r q 2 ' 7 w x u q r q w l p h p d [ l p x p l v z k h q w k h 2 ' 7 u h v l v w d q f h l v i x o o \ r q 7 k h 2 ' 7 u h i h u h q f h o r d g l v v k r z q l q figure 23. 39. + d o i f o r f n r x w s x w s d u d p h w h u v p x v w g h u d w h g e \ w k h d f w x d o t ( 5 5 3 ( 5 and t - , 7 ' 7 < z k h q l q s x w f o r f n m l w w h u l v s u h v h q w 7 k l v u h v x o w v l q h d f k s d u d p h w h u e h f r p l q j o d u j h u 7 k h s d u d p h w h u v t $ ' & 0 , 1 d q g t $ 2 ) 0 , 1 d u h h d f k u h t x l u h g w r e h g h u d w h g e \ v x e w u d f w l q j e r w k w ( 5- 5 3 ( 5 0 $ ; d q g t - , 7 ' 7 < 0 $ ; 7 k h s d u d p h w h u v t $ ' & 0 $ ; and t $ 2 ) 0 $ ; d u h u h t x l u h g w r e h g h u d w h g e \ v x e w u d f w l q j e r w k t ( 5- 5 3 ( 5 0 $ ; d q g t - , 7 ' 7 < 0 $ ; 40. 2 ' 7 w x u q r i i w l p h p l q l p x p l v z k h q w k h g h y l f h v w d u w v w r w x u q r i i 2 ' 7 u h v l v w d q f h 2 ' 7 w x u q r i i w l p h p d [ l p x p l v z k h q w k h 6 ' 5 $ 0 e x i i h u l v l q + , * + = 7 k h 2 ' 7 u h i h u h q f h o r d g l v v k r z q l q ) l j x u h 7 k l v r x w s x w o r d g l v x v h g i r u 2 ' 7 w l p l q j v v h h ) l j x u h 41. 3 x o v h z l g w k r i d q l q s x w v l j q d o l v g h i l q h g d v w k h z l g w k e h w z h h q w k h i l u v w f u r v v l q j r i 9 5 ( ) ' & d q g w k h f r q v h f x w l y h f u r v v l q j r i 9 5 ( ) ' & 42. 6 k r x o g w k h f o r f n u d w h e h o d u j h u w k d q t 5 ) & 0 , 1 d q $ 8 7 2 5 ( ) 5 ( 6 + f r p p d q g v k r x o g k d y h d w o h d v w r q h 1 2 3 f r p p d q g e h w z h h q l w d q g d q r w k h u $ 8 7 2 5 ( ) 5 ( 6 + f r p p d q g $ g g l w l r q d o o \ l i w k h f o r f n u d w h l v v o r z h u w k d q q v 0 + ] d o o 5 ( ) 5 ( 6 + f r p p d q g v v k r x o g e h i r o - o r z h g e \ d 3 5 ( & + $ 5 * ( $ / / f r p p d q g logic devices incorporated www.logicdevices.com 58 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product command and address setup, hold, and derating the total t , 6 v h w x s w l p h d q g t , + k r o g w l p h u h t x l u h g l v f d o f x o d w h g e \ d g g l q j w k h g d w d v k h h w t , 6 e d v h d q g t , + e d v h y d o x h v 7 d e o h v w r w k h ' t is and ' t , + g h u d w l q j y d o x h v 7 d e o h u h v s h f w l y h o \ 6 h w x s d q g k r o g w l p h v d u h e d v h g r q p h d v x u h p h q w v d w w k h g h y l f h 1 r w h w k d w d g g u h v v d q g f r q w u r o s l q v s u h v h q w w k h f d s d f l w d q f h r i p x o w l s o h g l h w r w k h v \ v w h p 7 k l v f d s d f l w d q f h l v o h v v w k d q w k h h t x l y d o h q w q x p e h u r i g l v f u h w h g h y l f h v g x h w r w k h k l j k h u o h y h o r i g l h l q w h j u d w l r q k r z h y h u l w p x v w e h d f f r x q w h g i r u z k h q g u l y l q j w k h v h s l q v 6 o h z u d w h v r q w k h v h s l q v z l o o e h v o r z h u w k d q s l q v z l w k r q o \ r q h g l h o r d g x q o h v v p h d v x u h v d u h p d g h w r l q f u h d v h w k h v w u h q j w k r i w k h v l j q d o g u l y h u d q g o r z h u w k h w u d f h l p s h g d q f h s u r s r u w l r q d o o \ r q v l j q d o v f r q q h f w l q j w r p x o w l s o h l q w h u q d o g l h $ o w k r x j k w k h w r w d o v h w x s w l p h i r u v o r z v o h z u d w h v p l j k w e h q h j d w l y h d y d o l g l q s x w v l j q d o l v v w l o o u h t x l u h g w r f r p s o h w h w k h w u d q v l w l r q d q g w r u h d f k 9 , + $ & 9 il $ & v h h ) l j x u h i r u l q s x w v l j q d o u h t x l u h p h q w v ) r u v o h z u d w h v z k l f k i d o o e h w z h h q w k h y d o x h v o l v w h g l q 7 d e o h d q g 7 d e o h w k h g h u d w l q j y d o x h v p d \ e h r e w d l q h g e \ o l q h d u l q w h u s r o d w l r q 6 h w x s t , 6 q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 5 ( ) ' & d q g w k h i l u v w f u r v v l q j r i 9 , + $ & 0 , 1 6 h w x s t , 6 q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 5 ( ) ' & d q g w k h i l u v w f u r v v l q j r i 9 il $ & 0 $ ; , i w k h d f w x d o v l j q d o l v d o z d \ v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q w k h v k d g h g v 9 5 ( ) ' & w r $ & u h j l r q w x v h w k h q r p l q d o v o h z u d w h i r u g h u d w l q j y d o x h v h h ) l j x u h , i w k h d f w x d o v l j q d o l v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q w k h v k d g h g v 9 5 ( ) ' & w r $ & u h j l r q w w k h v o h z u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h $ & o h y h o w r w k h ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h v h h ) l j x u h + r o g t , + q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 il ' & 0 $ ; d q g w k h i l u v w f u r v v l q j r i 9 5 ( ) ' & + r o g t , + q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 , + ' & 0 , 1 d q g w k h i l u v w f u r v v l q j r i 9 5 ( ) ' & , i w k h d f w x d o v l j q d o l v d o z d \ v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q w k h v k d g h g v ' & w r 9 5 ( ) ' & u h j l r q w x v h w k h q r p l q d o v o h z u d w h i r u g h u d w l q j y d o x h v h h ) l j x u h , i w k h d f w x d o v l j q d o l v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q w k h v k d g h g w ' & w r 9 5 ( ) ' & u h j l r q w w k h v o h z u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h ' & o h y h o w r w k h 9 5 ( ) ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h v h h ) l j x u h symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 units reference t is(base) t is(base) t ih(base)dc100 9 , + $ & 9 il $ & 9 , + $ & 9 il $ & 9 , + $ & 9 il $ & t able 48: c ommand and a ddress s etup and h old v alues r eferenced at 1v/ ns ? ac/dc based 600 600 600 600 600 - 600 600 - ps ps ps ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih 2.0 1.5 1.0 0.9 0.8 0.6 0.5 0.4 t able 49: d erating v alues for t is/ t ih ? ac175/dc100-b ased cmd/addr slew rate v/ns 88 59 0 -2 -6 -11 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 88 50 0 -2 -6 -11 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 88 59 0 -2 -6 -11 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 96 8 6 2 -3 -9 -54 58 42 8 4 -2 -8 -18 -32 -52 96 8 6 2 -3 -9 -54 66 50 16 12 6 0 -10 -24 -44 112 83 24 22 18 13 -11 -38 58 24 20 14 8 -2 -16 -36 120 91 32 30 26 21 15 -2 -30 84 68 34 30 24 18 8 -6 -26 128 99 40 38 34 29 23 5 -22 100 84 50 46 40 34 24 10 -10 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns ck, ck\ differential slew rate shaded cells indicate slew-rate combinations not supported ' t is, ' t ih derating (ps) - ac/dc-based, ac175 threshold; v ih (ac) = v ref (dc) + 175mv, v il (ac) = v ref (dc) - 175mv 600 600 600 - - - logic devices incorporated www.logicdevices.com 59 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih ' t is ' t ih 2.0 1.5 1.0 0.9 0.8 0.6 0.5 0.4 t able 50: d erating v alues for t is/ t ih ? ac150/dc100-b ased cmd/addr slew rate v/ns 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 83 58 8 8 8 8 -2 58 42 8 4 -2 -8 -18 -32 -52 91 66 16 16 16 16 15 6 -9 66 50 16 12 6 0 -10 -24 -44 99 24 24 24 24 23 14 -1 58 24 20 14 8 -2 -16 -36 82 32 32 32 32 31 22 84 68 34 30 24 18 8 -6 -26 115 90 40 40 40 40 39 30 15 100 84 50 46 40 34 24 10 -10 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns ck, ck\ differential slew rate ' t is, ' t ih derating (ps) - ac/dc-based, ac150 threshold; v ih (ac) = v ref (dc) + 150mv, v il (ac) = v ref (dc) - 150mv shaded cells indicate slew-rate combinations not supported slew rate (v/ns) t vac at 175mv(ps) t vac at 150mv(ps) >2.0 2.0 1.5 1.0 0.9 0.8 0.6 0.5 <0.5 163 162 161 159 155 150 150 t able 51: m inimum r equired t ime t v ac above v ih (ac) for a v alid t ransition 50 38 34 29 22 13 0 0 below vil(ac) logic devices incorporated www.logicdevices.com 60 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. both the clock and the strobe are drawn on different time scales. v ss setup slew rate risin g signal setup slew rate falling signal ?tf ?tr = = v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( dc ) max nominal slew rate v ref to ac region t vac t vac dqs dqs# ck# ck t is t ih t is t ih nominal slew rate v ref to ac region v ref ( dc ) - v il ( ac ) max ?tf v ih ( ac ) min - v ref ( dc ) ?tr f igure 25 - n ominal s lew r ate and t vac for t is (c ommand and a ddress ? c lock ) logic devices incorporated www.logicdevices.com 61 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 26 - n ominal s lew r ate for t ih (c ommand and a ddress ? c lock ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate falling signal hol d slew rate rising signal ?tr ?tf = = v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max nominal slew rate dc to v ref region dqs dqs# ck # ck t is t ih t is t ih dc to v ref region nominal slew rate v ref ( dc ) - v il ( dc ) max ?tr v ih ( dc ) min - v ref ( dc ) ?tf logic devices incorporated www.logicdevices.com 62 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 27 - t angent l ine for t is (c ommand and a ddress ? c lock ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss setup slew rate rising signal setup slew rate falling signal ?tf ?tr = = v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max tangent line v ref to ac region nominal line t vac t vac dqs dqs# ck # ck t is t ih t is t ih v ref to ac region tangent line nominal line tangent line (v ih [ dc ] min - v ref [ dc ]) ?tr tangent line (v ref [ dc ] - v il [ ac ] max) ?tf logic devices incorporated www.logicdevices.com 63 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 28 - t angent l ine for t ih (c ommand and a ddress ? c lock ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate falling signal ?tr = v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max tangent line dc to v ref region hol d slew rate rising signal = dqs dqs # ck# ck t is t ih t is t ih dc to v ref region tangent line nominal line nominal line ?tr tangent line (v ref [ dc ] - v il [ dc ] max) ?tr tangent line (v ih [ dc ] min - v ref [ dc ]) ?tf logic devices incorporated www.logicdevices.com 64 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product data setup, hold and derating the total t ' 6 v h w x s w l p h d q g t ' + k r o g w l p h u h t x l u h g l v f d o f x o d w h g e \ d g g l q j w k h g d w d v k h h w t ' 6 e d v h d q g t ' + e d v h y d o x h v v h h 7 d e o h w r w k h ' t ds and ' t ' + g h u d w l q j y d o x h v v h h 7 d e o h u h v s h f w l y h o \ $ o w k r x j k w k h w r w d o v h w x s w l p h i r u v o r z v o h z u d w h v p l j k w e h q h j d w l y h d y d o l g l q s x w v l j q d o l v v w l o o u h t x l u h g w r f r p s o h w h w k h w u d q v l w l r q d q g w r u h d f k 9 , + 9 il $ & ) r u v o h z u d w h v z k l f k i d o o e h w z h h q w k h y d o x h v o l v w h g l q 7 d e o h w k h g h u d w l q j y d o x h v p d \ e h r e w d l q h g e \ o l q h d u l q w h u s r o d w l r q 6 h w x s t ' 6 q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 5 ( ) ' & d q g w k h i l u v w f u r v v l q j r i 9 , + $ & 0 , 1 6 h w x s t ' 6 q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 5 ( ) ' & d q g w k h i l u v w f u r v v l q j r i 9 il $ & 0 $ ; , i w k h d f w x d o v l j q d o l v d o z d \ v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q w k h v k d g h g v 9 5 ( ) ' & w r $ & u h j l r q w x v h w k h q r p l q d o v o h z u d w h g h u d w l q j y d o x h v h h ) l j x u h , i w k h d f w x d o v l j q d o l v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q w k h v k d g h g v 9 5 ( ) ' & w r $ & u h j l r q w w k h v o h z u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h $ & o h y h o w r w k h ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h v h h ) l j x u h + r o g t ' + q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 il ' & 0 $ ; d q g w k h i l u v w f u r v v l q j r i 9 5 ( ) ' & + r o g t ' + q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 , + ' & 0 , 1 d q g w k h i l u v w f u r v v l q j r i 9 5 ( ) ' & , i w k h d f w x d o v l j q d o l v d o z d \ v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q w k h v k d g h g v ' & w r 9 5 ( ) ' & u h j l r q w x v h w k h q r p l q d o v o h z u d w h i r u g h u d w l q j y d o x h v h h ) l j x u h , i w k h d f w x d o v l j q d o l v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q w k h v k d g h g v ' & w r 9 5 ( ) ' & u h j l r q w w k h v o h z u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h v ' & w r 9 5 ( ) ' & u h j l r q w l v x v h g i r u w k h g h u d w l q j y d o x h v h h ) l j x u h symbol ddr3-1333 ddr3-1600 ddr3-1866 units reference t ds(base)ac175 t ds(base)ac175 t ds(base)dc150 t ds(base)dc150 9 , + $ & 9 il $ & 9 , + $ & 9 il $ & 9 , + $ & 9 il $ & 9 , + $ & 9 il $ & t able 52: d ata s etup and h old v alues at 1v/ ns (dqs x , dqs x \ at 2v/ ns ) - ac/dc b ased - - 30 65 ps ps ps ps - - 10 45 - - 10 45 ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh 2.0 1.5 1.0 0.9 0.8 0.6 0.5 0.4 t able 53: d erating v alue for t ds/ t dh ? ac175/dc100 - b ased dq slew rate v/ns 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns dqs, dqs# differential slew rate ? t ds, ? t dh derating (ps) ? ac175/d100-based shaded cells indicate slew-rate combinations not supported 88 59 0 50 34 0 88 59 0 -2 50 34 0 -4 88 59 0 -2 -6 50 34 0 -4 -10 8 6 2 -3 42 8 4 -2 -8 16 14 10 5 -1 16 12 6 0 -10 22 18 13 -11 20 14 8 -2 -16 26 21 15 -2 -30 24 18 8 -6 -26 29 23 5 -22 34 24 10 -10 ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh 2.0 1.5 1.0 0.9 0.8 0.6 0.5 0.4 t able 54: d erating v alue for t ds/ t dh ? ac150/dc100 - b ased dq slew rate v/ns 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns dqs, dqs# differential slew rate ? t ds, ? t dh derating (ps) ? ac150/dc100-based shaded cells indicate slew-rate combinations not supported logic devices incorporated www.logicdevices.com 65 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 50 0 50 34 0 50 0 0 50 34 0 -4 50 0 0 0 50 34 0 -4 -10 58 8 8 8 8 42 8 4 -2 -8 16 16 16 16 15 16 12 6 0 -10 24 24 24 23 14 20 14 8 -2 -16 32 32 31 22 24 18 8 -6 -26 40 39 30 15 34 24 10 -10 slew rate (v/ns) t vac at 175mv(ps) [min] t vac at 150mv(ps) [min] >2.0 2.0 1.5 1.0 0.9 0.8 0.6 0.5 <0.5 163 162 161 159 155 150 150 t able 55: r equired t ime t vac a bove v ih (ac) (b elow v il [ac]) for a v alid t ransition 50 38 34 29 22 13 0 0 logic devices incorporated www.logicdevices.com 66 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 29 - n ominal s lew r ate and t vac for t ds (dq ? s trobe ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss setup slew rate rising signal setup slew rate ?tf ?tr = = v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max nominal slew rate v ref to ac region t vac t vac t dh t ds dqs dqs# t dh t ds ck# ck v ref to ac region nominal slew rate v ih ( ac ) min - v ref ( dc ) ?tr v ref ( dc ) - v il ( ac ) max ?tf rising signal logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 30 - n ominal s lew r ate for t dh (dq ? s trobe ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hold slew rate falling signal hold slew rate rising signal ?tr ?tf = = v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max nominal slew rate dc to v ref region t dh t ds dqs dqs# t dh t ds ck# ck dc to v ref region nominal slew rate v ref ( dc ) - v il ( dc ) max ?tr v ih ( dc ) min - v ref ( dc ) ?tf logic devices incorporated www.logicdevices.com 68 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 31 - n ominal s lew r ate and t vac for t ds (dq ? s trobe ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss setup slew rate rising signal setup slew rate falling signal ?tf ?tr = = v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max tangent line v ref to ac region nominal line t vac t vac t dh t ds dqs dqs# t dh t ds ck# ck v ref to ac region tangent line nominal line ?tr tangent line (v ref [ dc ] - v il [ ac ] max) ?tf tangent line (v ih [ ac ] min - v ref [ dc ]) logic devices incorporated www.logicdevices.com 69 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 32 - n ominal s lew r ate for t dh (dq ? s trobe ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate falling signal ?tf ?tr = v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max tangent line dc to v ref region hol d slew rate = dqs dqs# ck# ck dc to v ref region tangent line nominal line nominal line tangent line (v ih [ dc ] min - v ref [ dc ]) ?tf tangent line (v ref [ dc ] - v il [ dc ] max) ?tr t ds t dh t ds t dh falling signal logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product p ackage o utline d imensions function symbol cycle cycle cs\ ras\ cas\ we\ ba [2:0] a n a 12 a 10 a [11,0:0] notes mode register set refresh self refresh entry self refresh exit single-bank precharge precharge all banks bank activate no operation device deselected power-down entry power-down exit zq calibration long zq calibration short 6 8 8 8 8 8 8 8 8 8 8 8 8 9 10 6 6,11 12 t able 56: t ruth t able - c ommand l l l l l l l l l l l l l l l l l l l + l l l l l l l l + + + + + + + + + + + + + ; + + l l l l l l + + + + + + + + + + + + + ; + + l + + l l + l l l l l l + + + + + + + ; l l % $ 9 9 9 9 % $ 9 % $ % $ % $ % $ % $ % $ % $ % $ % $ % $ % $ % $ % $ 9 ; 9 9 ; ; 9 9 9 9 9 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 9 ; 9 9 ; ; 9 9 9 9 9 9 l + 9 l + 9 l + 9 l + 9 ; 9 9 ; ; 9 9 9 l + l l l + + + l l l + + + 9 ; 9 9 + l 9 9 9 9 9 5 $ & $ & $ & $ & $ & $ & $ & $ & $ & $ & $ & $ & $ 9 ; 9 9 ; ; mrs 5 ( ) 6 5 ( 6 5 ; 3 5 ( 3 5 ( $ $ & 7 : 5 : 5 6 : 5 6 : 5 $ 3 : 5 $ 3 6 : 5 $ 3 6 rd rds4 rds8 5 ' $ 3 5 ' $ 3 6 5 ' $ 3 6 nop ' ( 6 3 ' ( 3 ' ; = 4 & / = 4 & 6 + + + l + + + + + + + + + + + + + + + + + + l + + + + l + + + + + + + + + + + + + + + + + + l + + + write write with auto precharge read read with auto precharge bl8mrs % & 0 5 6 % & 2 7 ) bl8otf bl8mrs % & 0 5 6 % & 2 7 ) bl8otf bl8mrs % & 0 5 6 % & 2 7 ) bl8otf bl8mrs % & 0 5 6 % & 2 7 ) bl8otf + l l + l + 9 + 9 + 9 + + 9 + 9 + 9 + 9 + 9 + 9 cke prev next 8. % x u v w 5 ( $ ' v r u : 5 , 7 ( v f d q q r w e h w h u p l q d w h g r u l q w h u u x s w h g 0 5 6 i l [ h g d q g 2 7 ) % / % & d u h g h i l q h g l q 0 5 9. 7 k h s x u s r v h r i w k h 1 2 3 f r p p d q g l v w r s u h y h q w w k h 6 ' 5 $ 0 i u r p u h j - l v w h u l q j d q \ x q z d q w h g f r p p d q g v $ 1 2 3 z l o o q r w w h u p l q d w h d q g r s h u d - w l r q w k d w l v l q h [ h f x w l r q 10. 7 k h ' ( 6 d q g 1 2 3 f r p p d q g v s h u i r u p v l p l o d u o \ 11. 7 k h 3 2 : ( 5 ' 2 : 1 p r g h g r h v q r w s h u i r u p d q \ 5 ( ) 5 ( 6 + r s h u d - tions. 12. = 4 & $ / , % 5 $ 7 , 2 1 / 2 1 * l v x v h g i r u h l w k h u = 4 , 1 7 i l u v w = 4 & / f r p - p d q g g x u l q j l q l w l d o l ] d w l r q r u = 4 2 3 ( 5 = 4 & / f r p p d q g d i w h u l q l w l d o l ] d - w l r q 1 2 7 ( 6 1. & r p p d q g v d u h g h i l q h g e \ v w d w h v r i & 6 ? 5 $ 6 ? & $ 6 ? : ( ? d q g & . ( d w w k h u l v l q j h g j h r i w k h f o r f n 7 k h 0 6 % r i % $ 5 $ d q g & $ d u h g h y l f h g h q v l w \ d q g f r q i l j x u d w l r q g h s h q g h q w 2. 5 ( 6 ( 7 ? l v / 2 : h q d e o h g d q g x v h g r q o \ i r u d v \ q f k u r q r x v 5 ( 6 ( 7 7 k x v 5 ( 6 ( 7 ? p x v w e h k h o g + , * + g x u l q j d q \ q r u p d o r s h u d w l r q 3. 7 k h v w d w h r i 2 ' 7 g r h v q r w d i i h f w w k h v w d w h v g h v f u l e h g l q w k l v w d e o h 4. 2 s h u d w l r q v d s s o \ w r w k h e d q n g h i l q h g e \ w k h e d q n d g g u h v v ) r u 0 5 6 % $ v h o h f w v r q h r i i r x u p r g h u h j l v w h u v 5. v 9 w p h d q v v + w r u v / w d g h i l q h g o r j l f o h y h o d q g v ; w p h d q v v ' r q u w & d u h w 6. 6 h h 7 d e o h i r u d g g l w l r q d o l q i r u p d w l r q r q & . ( w u d q v l w l r q 6 ( / ) 5 ( ) 5 ( 6 + h [ l w l v d v \ q f k u r q r x v commands truth table logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product current state 3 power-down self refresh bank(s) active reading writing precharging refreshing all banks idle t able 57: t ruth t able - cke l + l + l l l l l l (n-1) previous cycle 4 (n) present cycle 4 (ras\, cas\, we\, cs\) command 5 action 5 notes l l l + + + + + + + v ' r q u w & d u h w ' ( 6 r u 1 2 3 v ' r q u w & d u h w ' ( 6 r u 1 2 3 ' ( 6 r u 1 2 3 ' ( 6 r u 1 2 3 ' ( 6 r u 1 2 3 ' ( 6 r u 1 2 3 ' ( 6 r u 1 2 3 5 ( ) 5 ( 6 + 0 d l q w d l q 3 2 : ( 5 ' 2 : 1 3 2 : ( 5 ' 2 : 1 h [ l w 0 d l q w d l q 6 ( / ) 5 ( ) 5 ( 6 + 6 ( / ) 5 ( ) 5 ( 6 + h [ l w $ f w l y h 3 2 : ( 5 ' 2 : 1 h q w u \ 3 2 : ( 5 ' 2 : 1 h q w u \ 3 2 : ( 5 ' 2 : 1 h q w u \ 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 h q w u \ 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 h q w u \ 6 ( / ) 5 ( ) 5 ( 6 + 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,6 cke 4. & . ( q l v w k h o r j l f v w d w h r i & . ( d w f o r f n h g j h q & . ( q z d v w k h v w d w h r i & . ( d w w k h s u h y l r x v f o r f n h g j h 5. & 2 0 0 $ 1 ' l v w k h f r p p d q g u h j l v w h u h g d w w k h f o r f n h g j h p x v w e h d o h j d o f r p p d q g d v g h i l q h g l q 7 d e o h $ f w l r q l v d u h v x o w r i & 2 0- 0 $ 1 ' 2 ' 7 g r h v q r w d i i h f w w k h v w d w h v g h v f u l e h g l q w k l v w d e o h d q g l v not listed. 6. , g o h v w d w h d o o e d q n v d u h f o r v h g q r g d w d e x u v w v d u h l q s u r j u h v v & . ( l v + , * + d q g d o o w l p l q j v i u r p s u h y l r x v r s h u d w l r q v d u h v d w l v i l h g $ o o 6 ( / ) 5 ( ) 5 ( 6 + h [ l w d q g 3 2 : ( 5 ' 2 : 1 h [ l w s d u d p h w h u v d u h d o v r v d w l v i l h g 1 2 7 ( 6 1. $ o o v w d w h v d q g v h t x h q f h v q r w v k r z q d u h l o o h j d o r u u h v h u y h g x q o h v v h [ s o l f - l w o \ g h v f u l e h g h o v h z k h u h l q w k l v g r f x p h q w 2. t & . ( 0 , 1 p h d q v & . ( p x v w e h u h j l v w h u h g d w p x o w l s o h f r q v h f x w l y h s r v l - w l y h f o r f n h g j h v & . ( p x v w u h p d l q d w w k h y d o l g l q s x w o h y h o w k h h q w l u h w l p h l w w d n h v w r d f k l h y h w k h u h t x l u h g q x p e h u r i u h j l v w u d w l r q f o r f n v 7 k x v d i w h u d q \ & . ( w u d q v l w l r q & . ( p d \ q r w w u d q v l w l r q i u r p l w v y d o l g o h y h o g x u l q j w k h w l p h s h u l r g r i t , 6 t & . ( 0 , 1 t , + 3. & x u u h q w v w d w h 7 k h v w d w h r i w k h 6 ' 5 $ 0 l p p h g l d w h o \ s u l r u w r f o r f n h g j h n. deselect (des) 7 k h ' ( 6 f r p p d q g & 6 ? + , * + s u h y h q w v q h z f r p p d q g v i u r p e h l q j h [ h - f x w h g e \ w k h 6 ' 5 $ 0 2 s h u d w l r q v d o u h d g \ l q s u r j u h v v d u h q r w d i i h f w h g no operation (nop) 7 k h 1 2 3 f r p p d q g & 6 ? / 2 : s u h y h q w v x q z d q w h g f r p p d q g v i u r p e h l q j u h j l v w h u h g g x u l q j l g o h r u z d l w v w d w h v 2 s h u d w l r q v d o u h d g \ l q s u r j u h v v d u h q r w d i i h f w h g zq calibration zq calibration long (zqcl) 7 k h = 4 & / f r p p d q g l v x v h g w r s h u i r u p w k h l q l w l d o f d o l e u d w l r q g x u l q j d s r z h u x s l q l w l d o l ] d w l r q d q g u h v h w v h t x h q f h 7 k l v f r p p d q g p d \ e h l v v x h g d w d q \ w l p h e \ w k h f r q w u r o o h u g h s h q g l q j r q w k h v \ v w h p h q y l u r q p h q w 7 k h = 4 & / f r p p d q g w u l j j h u v w k h f d o l e u d w l r q h q j l q h l q v l g h w k h 6 ' 5 $ 0 $ i w h u f d o l e u d w l r q l v d f k l h y h g w k h f d o l e u d w h g y d o x h v d u h w u d q v i h u u h g i u r p w k h f d o l e u d w l r q h q j l q h w r w k h 6 ' 5 $ 0 , 2 z k l f k d u h u h i o h f w h g d v x s g d w h g 5 on and odt values. 7 k h 6 ' 5 $ 0 l v d o o r z h g d w l p l q j z l q g r z g h i l q h g e \ h l w k h u t = 4 , 1 , 7 r u t = 4 2 3 ( 5 w r s h u i r u p w k h i x o o f d o l e u d w l r q d q g w u d q v i h u r i y d o x h v : k h q = 4 & / l v l v v x h g g x u l q j w k h l q l w l d o l ] d w l r q v h t x h q f h w k h w l p l q j s d u d p h w h u w = 4 , 1 , 7 p x v w e h v d w l v i l h g : k h q l q l w l d o l ] d w l r q l v f r p s o h w h v x e v h t x h q w = 4 & / f r p p d q g v u h t x l u h w k h w l p l q j s d u d p h w h u t = 4 2 3 ( 5 w r e h v d w l v i l h g zq calibration short (zqcs) 7 k h = 4 & 6 f r p p d q g l v x v h g w r s h u i r u p s h u l r g l f f d o l e u d w l r q v w r d f f r x q w i r u v p d o o y r o w d j h d q g w h p s h u d w x u h y d u l d w l r q v 7 k h v k r u w h u w l p l q j z l q g r z l v s u r y l g h g w r s h u i r u p w k h u h g x f h g f d o l e u d w l r q d q g w u d q v i h u r i y d o x h v d v g h i l q h g e \ w l p l q j s d u d p h w h u t = 4 & 6 $ = 4 & 6 f r p p d q g f d q h i i h f w l y h o \ f r u u h f w d p l q l p x p r i r on and r tt l p s h g d q f h h u u r u v z l w k l q f o r f n f \ f o h v d v v x p l q j w k h p d [ l p x p v h q v l w l y l w l h v v s h f l i l h g l q 7 d e o h d q g 7 d e o h logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product activate 7 k h $ & 7 , 9 $ 7 ( f r p p d q g l v x v h g w r r s h q r u $ & 7 , 9 $ 7 ( d u r z l q d s d u w l f x o d u e d q n i r u d v x e v h t x h q w d f f h v v 7 k h y d o x h r q w k h % $ > @ l q s x w v v h o h f w v w k h e d q n d q g w k h d g g u h v v s u r y l g h g r q l q s x w v $ > q @ v h o h f w v w k h u r z 7 k l v u r z u h p d l q v r s h q r u $ & 7 , 9 ( i r u d f f h v v h v x q w l o d 3 5 ( - & + $ 5 * ( f r p p d q g l v l v v x h g w r w k d w e d q n $ 3 5 ( & + $ 5 * ( f r p p d q g p x v w e h l v v x h g e h i r u h r s h q l q j d g l i i h u h q w u r z l q w k h v d p h e d q n read 7 k h 5 ( $ ' f r p p d q g l v x v h g w r l q l w l d w h d e x u v w 5 ( $ ' d f f h v v w r d q $ & 7 , 9 ( u r z 7 k h d g g u h v v s u r y l g h g r q l q s x w v $ > @ v h o h f w v w k h v w d u w l q j f r o x p q d g g u h v v g h s h q g l q j r q w k h e x u v w o h q j w k d q g e x u v w w \ s h v h o h f w h g v h h w d e o h 7 k h y d o x h r q l q s x w $ g h w h u p l q h v z k h w k h u r u q r w d x w r s u h f k d u j h l v x v h g , i d x w r s u h f k d u j h l v v h o h f w h g w k h u r z e h l q j d f f h v v h g z l o o e h 3 5 ( - & + $ 5 * ( ' d w w k h h q g r i w k h 5 ( $ ' e x u v w , i $ 8 7 2 3 5 ( & + $ 5 * ( l v q r w v h o h f w h g w k h u r z z l o o u h p d l q r s h q i r u v x e v h t x h q w d f f h v v h v 7 k h y d o x h r q l q s x w $ l i h q d e o h g l q w k h 0 2 ' ( 5 ( * , 6 7 ( 5 z k h q w k h 5 ( $ ' f r p p d q g l v l v v x h g g h w h u p l q h v z k h w k h u % & f k r s r u % / l v x v h g $ i w h u d 5 ( $ ' f r p p d q g l v l v v x h g w k h 5 ( $ ' e x u v w p d \ q r w e h l q w h u u x s w h g $ v x p p d u \ r i 5 ( $ ' f r p p d q g v l v v k r z q l q 7 d e o h t able 58: r ead c ommand s ummary function symbol cycle cycle cs\ ras\ cas\ we\ ba [2:0] a n a 12 a 10 a [11,0:0] notes l l l l l l + + + + + + l l l l l l + + + + + + % $ % $ % $ % $ % $ % $ 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 9 l + 9 l + l l l + + + & $ & $ & $ & $ & $ & $ rd rds4 rds8 5 ' $ 3 5 ' $ 3 6 5 ' $ 3 6 + + + + + + cke prev next read read with auto precharge bl8mrs % & 0 5 6 % & 2 7 ) bl8otf bl8mrs % & 0 5 6 % & 2 7 ) bl8otf write 7 k h : 5 , 7 ( f r p p d q g l v x v h g w r l q l w l d w h d e x u v w : 5 , 7 ( d f f h v v w r d q $ & 7 , 9 ( u r z 7 k h y d o x h r q w k h % $ > @ l q s x w v v h o h f w v w k h e d q n 7 k h y d o x h r q l q s x w $ g h w h u p l q h v z k h w k h u r u q r w $ 8 7 2 3 5 ( & + $ 5 * ( l v x v h g 7 k h y d o x h r q l q s x w $ l i h q d e o h g l q w k h 0 2 ' ( 5 ( * , 6 7 ( 5 > 0 5 @ z k h q w k h : 5 , 7 ( f r p p d q g l v l v v x h g g h w h u p l q h v z k h w k h u % & f k r s r u % / l v x v h g 7 k h : 5 , 7 ( f r p p d q g v x p p d u \ l v v k r z q l q 7 d e o h t able 59: w rite c ommand s ummary function symbol cycle cycle cs\ ras\ cas\ we\ ba [2:0] a n a 12 a 10 a [11,0:0] notes l l l l l l + + + + + + l l l l l l l l l l l l % $ % $ % $ % $ % $ % $ 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 5 ) 8 9 l + 9 l + l l l + + + & $ & $ & $ & $ & $ & $ : 5 : 5 6 : 5 6 : 5 $ 3 : 5 $ 3 6 : 5 $ 3 6 + + + + + + cke prev next write write with auto precharge bl8mrs % & 0 5 6 % & 2 7 ) bl8otf bl8mrs % & 0 5 6 % & 2 7 ) bl8otf logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 7 k h 3 5 ( & + $ 5 * ( f r p p d q g l v x v h g w r ' ( $ & 7 , 9 $ 7 ( w k h r s h q u r z l q d s d u w l f x o d u e d q n r u l q d o o e d q n v 7 k h e d q n v d u h d y d l o d e o h i r u d v x e v h t x h q w u r z d f f h v v d w d v s h f l i l h g w l p h t 5 3 d i w h u w k h 3 5 ( & + $ 5 * ( f r p p d q g l v l v v x h g h [ f h s w l q w k h f d v h r i f r q f x u u h q w $ 8 7 2 3 5 ( & + $ 5 * ( $ 5 ( $ ' r u : 5 , 7 ( f r p p d q g w r d g l i i h u h q w e d q n l v d o o r z h g g x u l q j f r q f x u u h q w $ 8 7 2 3 5 ( & + $ 5 * ( d v o r q j d v l w g r h v q r w l q w h u u x s w w k h g d w d w u d q v i h u l q w k h f x u- u h q w e d q n d q g g r h v q r w y l r o d w h d q \ r w k h u w l p l q j s d u d p h w h u v , q s x w $ g h w h u p l q h v z k h w k h u r q h r u d o o e d q n v d u h s u h f k d u j h g , q w k h f d v h z k h u h r q o \ r q h e d q n l v u h f k d u j h g , q s x w v % $ > @ v h o h f w w k h e d q n r w k h u z l v h % $ > @ d u h w u h d w h g d v v ' r q u w & d u h w $ i w h u d e d q n l v 3 5 ( & + $ 5 * ( ' l w l v l q w k h l g o h v w d w h d q g p x v w e h d f w l y d w h g s u l r u w r d q \ 5 ( $ ' r u : 5 , 7 ( f r p- p d q g v e h l q j l v v x h g w r w k d w e d q n $ 3 5 ( & + $ 5 * ( f r p p d q g l v w u h d w h g d v d 1 2 3 l i w k h u h l v q r r s h q u r z l q w k d w e d q n l g o h v w d w h r u l i w k h s u h y l - r x v o \ r s h q u r z l v d o u h d g \ l q w k h s u r f h v v r i s u h f k d u j l q j + r z h y h u w k h 3 5 ( & + $ 5 * ( s h u l r g l v g h w h u p l q h g e \ w k h o d v w 3 5 ( & + $ 5 * ( f r p p d q g l v v x h g w r w k h e d q n precharge 5 ( ) 5 ( 6 + l v x v h g g x u l q j q r u p d o r s h u d w l r q r i w k h 6 ' 5 $ 0 d q g l v d q d o r j r x v w r & $ 6 ? e h i r u h 5 $ 6 ? & % 5 u h i u h v k r u $ 8 7 2 5 ( ) 5 ( 6 + 7 k l v f r p p d q g l v q r q s h u v l v w h q w v r l w p x v w e h l v v x h g h d f k w l p h d 5 ( ) 5 ( 6 + l v u h t x l u h g 7 k h d g g u h v v l q j l v j h q h u d w h g e \ w k h l q w h u q d o 5 ( ) 5 ( 6 + f r p p d q g 7 k h 6 ' 5 $ 0 u h t x l u h v 5 ( ) 5 ( 6 + f \ f o h v d w d q d y h u d j h l q w h u y d o r i ? v p d [ l - p x p z k h q 7 $ d ? & r u ? v 0 $ ; z k h q 7 $ d ? & 7 k h 5 ( ) 5 ( 6 + s h u l r g e h j l q v z k h q w k h 5 ( ) 5 ( 6 + f r p p d q g l v u h j l v w h u h g d q g h q g v t 5 ) & 0 , 1 later. 7 r d o o r z i r u l p s u r y h g h i i l f l h q f \ l q v f k h g x o l q j d q g v z l w f k l q j e h w z h h q w d v n v v r p h i o h [ l e l o l w \ l q w k h d e v r o x w h 5 ( ) 5 ( 6 + l q w h u y d o l v s u r y l g h g $ p d [ l p x p r i h l j k w 5 ( ) 5 ( 6 + f r p p d q g v f d q e h s r v w h g w r d q \ j l y h q 6 ' 5 $ 0 p h d q- l q j w k d w w k h p d [ l p x p d e v r o x w h l q w h u y d o e h w z h h q d q \ 5 ( ) 5 ( 6 + f r p p d q g d q g w k h q h [ w 5 ( ) 5 ( 6 + f r p p d q g l v q l q h w l p h v w k h p d [ l p x p d y h u d j h l q w h u y d o u h i u h v k u d w h 6 ( / ) 5 ( ) 5 ( 6 + p d \ e h h q w h u h g z l w k x s w r h l j k w 5 ( ) 5 ( 6 + f r p p d q g v e h l q j s r v w h g $ i w h u h [ l w l q j 6 ( / ) 5 ( ) 5 ( 6 + z k h q h q w h u h g z l w k s r v w h g 5 ( ) 5 ( 6 + f r p p d q g v d g g l w l r q d o s r v w l q j r i 5 ( ) 5 ( 6 + f r p p d q g v l v d o o r z h g w r w k h h [ w h q w w k h p d [ l p x p q x p e h u r i f x p x o d w l y h s r v w h g 5 ( ) 5 ( 6 + f r p p d q g v e r w k s u h d q g s r v w 6 ( / ) 5 ( ) 5 ( 6 + g r h v q r w h [ f h h g h l j k w 5 ( ) 5 ( 6 + f r p p d q g v refresh f igure 33 - r efresh m ode notes: 1. nop commands are shown for ease of illustration; other valid commands may be possible at these times. cke must be active during the precharge, activate, and refresh commands, but may be inactive at other times (see power-down mode on page 153). nop 1 nop 1 nop 1 pre ra bank(s) 3 ba ref nop 1 ref 2 nop 1 act nop 1 one bank all banks t ck t ch t cl ra t rfc 2 t rp t rfc (min) t0 t1 t2 t3 t4 ta0 tb0 ta1 tb 1 tb2 dont care indicates a break in time scale valid 1 valid 1 valid 1 ck ck# command cke address a10 ba[2:0] dq 4 dm 4 dqs, dqs# 4 logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 7 k h 6 ( / ) 5 ( ) 5 ( 6 + f r p p d q g l v x v h g w r u h w d l q g d w d l q w k h 6 ' 5 $ 0 h y h q l i w k h u h v w r i w k h v \ v w h p l v s r z h u h g g r z q : k h q l q w k h 6 ( / ) 5 ( ) 5 ( 6 + p r g h w k h 6 ' 5 $ 0 u h w d l q v g d w d z l w k r x w h [ w h u q d o f o r f n l q j 7 k h 6 ( / ) 5 ( ) 5 ( 6 + p r g h l v d o v r d f r q y h q l h q w p h w k r g x v h g w r h q d e o h g l v d e o h w k h ' / / d v z h o o d v w r f k d q j h w k h f o r f n i u h t x h q f \ z l w k l q w k h d o o r z h g v \ q f k u r q r x v r s h u d w l q j u d q j h $ o o s r z h u v x s s o \ l q s x w v l q f o x g l q j 9 5 ( ) & $ d q g 9 5 ( ) ' 4 p x v w e h p d l q w d l q h g d w y d o l g o h y h o v x s r q h q w u \ h [ l w d q g g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h r s h u d w l r q $ o o s r z h u v x s s o \ l q s x w v l q f o x g l q j 9 5 ( ) & $ d q g 9 5 ( ) ' 4 p x v w e h p d l q w d l q h g d w y d o l g o h y h o v x s r q h q w u \ h [ l w d q g g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h x q g h u f h u w d l q f r q g l w l r q v x 9 v v 9 5 ( ) ' 4 9 dd l v p d l q w d l q h g x 9 5 ( ) ' 4 l v y d o l g d q g v w d e o h s u l r u w r & . ( j r l q j e d f n + , * + x 7 k h i l u v w : 5 , 7 ( r s h u d w l r q p d \ q r w r f f x u h d u o l h u w k d q f o r f n v d i w h u 9 5 ( ) ' 4 is valid x $ o o r w k h u 6 ( / ) 5 ( ) 5 ( 6 + p r g h h [ l w w l p h u h t x l u h p h q w v d u h p h w self refresh , i w k h ' / / l v g l v d e o h g e \ w k h 0 2 ' ( 5 ( * , 6 7 ( 5 0 5 > @ f d q e h v z l w f k h g g x u l q j l q l w l d o l ] d w l r q r u o d w h u w k h 6 ' 5 $ 0 l v w d u j h w h g e x w q r w j x d u d q w h h g w r r s h u d w h v l p l o d u o \ w r w k h 1 2 5 0 $ / p r g h z l w k d i h z q r w d e o h h [ f h s w l r q v x 7 k h 6 ' 5 $ 0 v x s s r u w v r q o \ r q h y d o x h r i & $ 6 o d w h q f \ & / d q g r q h y d o x h r i & $ 6 : 5 , 7 ( o d w h q f \ & : / x ' / / ' , 6 $ % / ( p r g h d i i h f w v w k h 5 ( $ ' g d w d f o r f n w r g d w d v w u r e h u h o d w l r q v k l s t ' 4 6 & . e x w q r w w k h 5 ( $ ' g d w d w r g d w d v w u r e h u h o d w l r q v k l s t dqsq, t 4 + 6 s h f l d o d w w h q w l r q l v q h h g h g w r o l q h w k h 5 ( $ ' g d w d x s z l w k w k h f r q w u r o o h u w l p h g r p d l q z k h q w k h ' / / l v g l v d e o h g x , q 1 2 5 0 $ / r s h u d w l r q ' / / r q t ' 4 6 & . v w d u w v i u r p w k h u l v l q j f o r f n h g j h $ / & / f \ f o h v d i w h u w k h 5 ( $ ' f r p p d q g , q ' / / ' , 6 $ % / ( p r g h t ' 4 6 & . v w d u w v $ / & / y f \ f o h v d i w h u w k h 5 ( $ ' f r p p d q g $ g g l w l r q d o o \ z l w k w k h ' / / g l v d e o h g w k h y d o x h r i t ' 4 6 & . f r x o g e h larger than t & . 7 k h 2 ' 7 i h d w x u h l v q r w v x s s r u w h g g x u l q j ' / / ' , 6 $ % / ( p r g h l q f o x g l q j g \ q d p l f 2 ' 7 7 k h 2 ' 7 u h v l v w r u v p x v w e h g l v d e o h g e \ f r q w l q x r x v o \ u h j l v w h u l q j w k h 2 ' 7 e d o o / 2 : e \ s u r j u d p p l q j 5 tt _norm mr1[9,6,2] and r tt b : 5 0 5 > @ w r v w z k l o h l q ' / / ' , 6 $ % / ( p r g h 6 s h f l i l f v w h s v p x v w e h i r o o r z h g w r v z l w f k e h w z h h q w k h ' / / h q d e o h d q g ' / / ' , 6 $ % / ( p r g h v g x h w r d j d s l q w k h d o o r z h g f o r f n u d w h v e h w z h h q w k h w z r p r g h v t & . > $ 9 * @ 0 $ ; d q g t & . > ' / / ' , 6 $ % / ( @ 0 , 1 u h v s h f w l y h o \ 7 k h r q o \ w l p h w k h f o r f n l v d o o r z h g w r f u r v v w k l v f o r f n u d w h j d s l v g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h 7 k x v w k h u h t x l u h g s u r f h g x u h i r u v z l w f k l q j i u r p w k h ' / / ( 1 $ % / ( w r ' / / ' , 6 $ % / ( p r g h l v w r f k d q j h i u h t x h q f \ f x u l q j v h o i u h i u h v k v h h ) l j x u h 1. 6 w d u w l q j i u r p w k h , ' / ( v w d w h d o o e d q n v d u h 3 5 ( & + $ 5 * ( ' d o o w l p l q j v d u h i x o i l o o h g 2 ' 7 l v w x u q h g r i i d q g 5 tt _nom and r tt b : 5 d u h + , * + = v h w 0 5 > @ w r v w w r ' , 6 $ % / ( w k h ' / / 2. ( q w h u 6 ( / ) 5 ( ) 5 ( 6 + p r g h d i w h u t 0 2 ' k d v e h h q v d w l v i l h g 3. $ i w h u t & . 6 5 ( l v v d w l v i l h g f k d q j h w k h i u h t x h q f \ w r w k h g h v l u h g f o r f n u d w h 4. 6 ( / ) 5 ( ) 5 ( 6 + p d \ e h h [ l w h g z k h q w k h f o r f n l v v w d e o h g z l w k w k h q h z i u h t x h q f \ i r u t & . 6 5 ; 5. 7 k h 6 ' 5 $ 0 z l o o e h u h d g \ i r u l w v q h [ w f r p p d q g l q w k h ' / / ' , 6 $ % / ( p r g h d i w h u w k h j u h d w h u r i t mrd or t 0 2 ' k d v e h h q v d w l v i l h g $ = 4 & / f r p p d q g v k r x o g e h l v v x h g z l w k d s s u r s u l d w h w l p l q j p h w d v z h o o dll disable mode logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 34 - dll e nable m ode to dll d isable m ode command t0 t1 ta0 ta1 tb 0 tc0 7 6 td 0 td 1 te0 te1 tf0 ck ck# odt 9 vali d 1 don t care vali d 1 sre 3 nop mrs 2 nop srx 4 mrs 5 vali d 1 nop nop indicates a break in time scale t mod t cksre t mod t xs t ckesr cke t cksrx 8 1 2 7 ( 6 1. $ q \ y d o l g f r p p d q g 2. ' l v d e o h ' / / e \ v h w w l q j 0 5 > @ w r v w 3. : d l w t ; 6 w k h q v h w 0 5 > @ w r v w w r h q d e o h ' / / 4. : d l w t 0 5 ' w k h q v h w 0 5 > @ w r v w w r e h j l q ' / / 5 ( 6 ( 7 5. : d l w t 0 5 ' x s g d w h u h j l v w h u v & / & : / d q g z u l w h u h f r y h u \ p d \ e h q h f h v v d u \ 6. : d l w t 0 2 ' d q \ y d o l g f r p p d q g 6 w d u w l q j z l w k w k h l g o h v w d w h 8. & k d q j h i u h t x h q f \ 9. & o r f n p x v w e h v w d e o h d w o h d v w t & . 6 5 ; 10. 6 w d w l f / 2 : l q f d v h 5 tt _nom or r tt b : 5 l v h q d e o h g r w k h u z l v h v w d w l f / 2 : r u + , * + $ v l p l o d u s u r f h g x u h l v u h t x l u h g i r u v z l w f k l q j i u r p w k h ' / / g l v d e o h p r g h e d f n w r w k h ' / / h q d e o h p r g h 7 k l v d o v r u h t x l u h v f k d q j l q j w k h i u h t x h q f \ g x u l q j v h o i u h i u h v k p r g h v h h ) l j x u h r q s d j h 6 w d u w l q j i u r p w k h l g o h v w d w h d o o e d q n v d u h s u h f k d u j h g d o o w l p l q j v d u h i x o i l o o h g 2 ' 7 l v w x u q h g r i i d q g 5 tt _nom and r tt b : 5 d u h + l j k = h q w h u v h o i u h i u h v k p r g h $ i w h u t & . 6 5 ( l v v d w l v i l h g f k d q j h w k h i u h t x h q f \ w r w k h q h z f o r f n u d w h 6 h o i u h i u h v k p d \ e h h [ l w h g z k h q w k h f o r f n l v v w d e o h z l w k w k h q h z i u h t x h q f \ i r u t & . 6 5 ; $ i w h u t ; 6 l v v d w l v i l h g x s g d w h w k h p r g h u h j l v w h u v z l w k w k h d s s u r s u l d w h y d o x h v $ w d p l q l p x p v h w 0 5 > @ w r v w w r h q d e o h w k h ' / / : d l w t 0 5 ' w k h q v h w 0 5 > @ w r v w w r h q d e o h ' / / 5 ( 6 ( 7 $ i w h u d q r w k h u t 0 5 ' g h o d \ l v v d w l v i l h g w k h q x s g d w h w k h u h p d l q l q j p r g h u h j l v w h u v z l w k w k h d s s u r s u l d w h y d o x h v 7 k h ' 5 $ 0 z l o o e h u h d g \ i r u l w v q h [ w f r p p d q g l q w k h ' / / h q d e o h p r g h d i w h u w k h j u h d w h u r i t mrd or t 0 2 ' k d v e h h q v d w l v i l h g + r z h y h u e h i r u h d s s o \ l q j d q \ f r p p d q g r u i x q f w l r q u h t x l u l q j d o r f n h g ' / / d g h o d \ r i t ' / / . d i w h u ' / / 5 ( 6 ( 7 p x v w e h v d w l v i l h g $ = 4 & / f r p p d q g v k r x o g e h l v v x h g z l w k w k h d s s u r s u l d w h w l p l q j v p h w d v z h o o logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 35- dll d isable m ode to dll e nable m ode indicates a break in time scale t c t dllk cke t0 t a 0t a 1tb0 t c 0t c 1td0t e 0 tf0 t g 0 ck ck# odt 10 sre 1 nop command nop srx 2 mrs 3 mrs 4 mrs 5 vali d 6 vali d don t care 8 7 t ck sr e th0 t cksrx 9 odtl off + 1 t ck t xs t mrd t mrd kesr 1 2 7 ( 6 1. ( q w h u 6 ( / ) 5 ( ) 5 ( 6 + 2. ( [ l w 6 ( / ) 5 ( ) 5 ( 6 + 3. : d l w t ; 6 w k h q v h w 0 5 > @ w r v w w r h q d e o h ' / / 4. : d l w t 0 5 ' w k h q v h w 0 5 > @ w r v w w r e h j l q ' / / 5 ( 6 ( 7 5. : d l w t 0 5 ' x s g d w h u h j l v w h u v & / & : / d q g z u l w h u h f r y h u \ p d \ e h q h f h v v d u \ 6. : d l w t 0 2 ' d q \ y d o l g f r p p d q g 6 w d u w l q j z l w k w k h l g o h v w d w h 8. & k d q j h i u h t x h q f \ 9. & o r f n p x v w e h v w d e o h d w o h d v w t & . 6 5 ; 10. 6 w d w l f / 2 : l q f d v h 5 tt _nom or r tt b : 5 l v h q d e o h g r w k h u z l v h v w d w l f / 2 : r u + , * + 7 k h f o r f n i u h t x h q f \ u d q j h i r u w k h ' / / g l v d e o h p r g h l v v s h f l i l h g e \ w k h s d u d p h w h u t & . ' / / b ' , 6 ' x h w r o d w h q f \ f r x q w h u d q g w l p l q j u h v w u l f w l r q v r q o \ & / d q g & : / d u h v x s s r u w h g ' / / g l v d e o h p r g h z l o o d i i h f w w k h u h d g g d w d f o r f n w r g d w d v w u r e h u h o d w l r q v k l s t ' 4 6 & . e x w q r w w k h g d w d v w u r e h w r g d w d u h o d w l r q v k l s t dqsq, t 4 + 6 s h f l d o d w w h q - w l r q l v q h h g h g w r w k h f r q w u r o o h u w l p h g r p d l q & r p s d u h g w r w k h ' / / r q p r g h z k h u h t ' 4 6 & . v w d u w v i u r p w k h u l v l q j f o r f n h g j h $ / & / f \ f o h v d i w h u w k h 5 ( $ ' f r p p d q g w k h ' / / g l v d e o h p r g h t ' 4 6 & . v w d u w v $ / & / f \ f o h v d i w h u w k h 5 ( $ ' f r p p d q g v h h ) l j x u h r q s d j h : 5 , 7 ( r s h u d w l r q v i x q f w l r q v l p l o d u o \ e h w z h h q w k h ' / / h q d e o h d q g ' / / g l v d e o h p r g h v k r z h y h u 2 ' 7 i x q f w l r q d o l w \ l v q r w d o o r z h g z l w k ' / / g l v d e o h p r g h logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 36 - dll d isable t dqsck t iming t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 don t care transitioning data vali d nop read nop nop nop nop nop nop nop nop nop ck ck # command add ress di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 dq bl8 dll on dqs, dqs# dll on dq bl8 dll disable dqs, dqs# dll off dq bl8 dll disable dqs, dqs# dll off rl = al + c l = 6 (c l = 6, al = 0) c l = 6 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 t dqsck ( dll _ dis ) min t dqsck ( dll _ dis ) max rl (dll disable) = al + (c l - 1) = 5 : k h q w k h ' ' 5 6 ' 5 $ 0 l v l q l w l d o l ] h g l w u h t x l u h v w k h f o r f n w r e h v w d e o h g x u l q j p r v w 1 2 5 0 $ / v w d w h v r i r s h u d w l r q 7 k l v p h d q v w k d w d i w h u w k h f o r f n i u h t x h q f \ k d v e h h q v h w w r w k h v w d e o h v w d w h w k h f o r f n s h u l r g l v q r w d o o r z h g w r g h y l d w h h [ f h s w z k d w l v d o o r z h g i r u e \ w k h f o r f n m l w w h u d q g v s u h d g v s h f w u x p f o r f n l q j 6 6 & v s h f l i l f d w l r q v 7 k h l q s x w f o r f n i u h t x h q f \ f d q e h f k d q j h g i u r p r q h v w d e o h f o r f n u d w h w r d q r w k h u x q g h u w z r f r q g l w l r q v 6 ( / ) 5 ( ) 5 ( 6 + p r g h d q g 3 5 ( & + $ 5 * ( s r z h u g r z q p r g h 2 x w v l g h r i w k h v h w z r p r g h v l w l v l o o h j d o w r f k d q j h w k h f o r f n i u h t x h q f \ ) r u w k h 6 ( / ) 5 ( ) 5 ( 6 + p r g h f r q g l w l r q z k h q w k h ' ' 5 6 ' 5 $ 0 k d v e h h q v x f f h v v i x o o \ s o d f h g l q w r 6 ( / ) 5 ( ) 5 ( 6 + p r g h d q g t & . 6 5 ( k d v e h h q v d w l v i l h g w k h v w d w h r i w k h f o r f n e h f r p h v d v ' r q u w & d u h w : k h q w k h f o r f n e h f r p h v d v ' r q u w & d u h w f k d q j l q j w k h f o r f n i u h t x h q f \ l v s h u p l v v l e o h s u r y l g h g w k h q h z f o r f n i u h t x h q f \ l v v w d e o h s u l r u w r t & . 6 5 ; : k h q h q w h u l q j d q g h [ l w l q j v h o i u h i u h v k p r g h i r u w k h v r o h s x u s r v h r i f k d q j l q j w k h f o r f n i u h t x h q f \ w k h 6 ( / ) 5 ( ) 5 ( 6 + h q w u \ d q g h [ l w v s h f l i l f d w l r q v p x v w v w l o o e h p h w 7 k h 3 5 ( & + $ 5 * ( s r z h u g r z q p r g h f r q g l w l r q l v z k h q w k h ' ' 5 6 ' 5 $ 0 l v l q 3 5 ( & + $ 5 * ( s r z h u g r z q p r g h h l w k h u i d v w h [ l w p r g h r u v o r z h [ l w p r g h ( l w k h u 2 ' 7 p x v w e h d w d o r j l f / 2 : r u 5 tt _nom and r tt b : 5 p x v w e h g l v d e o h g y l d 0 5 d q g 0 5 7 k l v h q v x u h v 5 tt _nom and r tt b : 5 d u h l q d q r i i v w d w h s u l r u w r h q w h u l q j 3 5 ( & + $ 5 * ( s r z h u g r z q p r g h z k l o h p d l q w d l q l q j & . ( d w d o r j l f / 2 : $ p l q l p x p r i t & . 6 5 ( p x v w r f f x u d i w h u & . ( j r h v / 2 : e h i r u h w k h f o r f n i u h t x h q f \ f d q f k d q j h 7 k h ' ' 5 6 ' 5 $ 0 l q s x w f o r f n i u h t x h q f \ l v d o o r z h g w r f k d q j h r q o \ z l w k l q w k h p l q l p x p d q g p d [ l p x p r s h u d w l q j i u h t x h q f \ v s h f l - i l h g i r u w k h s d u w l f x o d u v s h h g w h p s h u d w x u h j u d g h t & . > $ 9 * @ 0 , 1 w r t & . > $ 9 * @ 0 $ ; g h y l f h ' x u l q j w k h l q s x w f o r f n i u h t x h q f \ f k d q j h & . ( p x v w e h k h o g d w d v w d e o h / 2 : o h y h o : k h q w k h l q s x w f o r f n i u h t x h q f \ l v f k d q j h g d v w d e o h f o r f n p x v w e h s u r y l g h g w r w k h 6 ' 5 $ 0 t & . 6 5 ; e h i r u h 3 5 ( & + $ 5 * ( s r z h u g r z q p d \ e h h [ l w h g $ i w h u 3 5 ( & + $ 5 * ( s r z h u g r z q l v h [ l w h g d q g t ; 3 k d v e h h q v d w l v i l h g w k h ' / / p x v w e h u h v h w y l d w k h 0 5 6 ' h s h q g l q j r q w k h q h z f o r f n i u h t x h q f \ d g g l w l r q d o 0 5 6 f r p p d q g v p d \ q h h g w r e h l v v x h g ' x u l q j w k h ' / / o r f n w l p h 5 tt _nom and r tt b : 5 p x v w u h p d l q l q d q r i i v w d w h $ i w h u w k h ' / / o r f n w l p h w k h 6 ' 5 $ 0 l v u h d g \ w r r s h u d w h z l w k d q h z f o r f n i u h t x h q f \ s h u l r g 7 k l v s u r f h v v l v g h s l f w h g l q ) l j x u h input clock frequency change logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 37- c hange f requency d uring p recharge p ower -d own ck ck# command nop nop nop address cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 ta0 tc0 tb0 t2 dont care t cke t xp mrs dll reset valid valid nop t ch t ih t is t cl tc1 td0 te1 td1 t cksre t ch b t cl b t ck b t ch b t cl b t ck b t ch b t cl b t ck b t cpded odt nop te0 previous clock frequency new clock fre quency frequency change indicates a break in time scale t ih t is t ih t is t dllk t aofpd/ t aof t cksrx high-z high-z 1 2 7 ( 6 1. $ s s o l f d e o h i r u e r w k v o r z h [ l w d q g i d v w h [ l w s u h f k d u j h s r z h u g r z q p r g h v 2. t $ 2 ) 3 ' d q g t $ 2 ) p x v w e h v d w l v i l h g d q g r x w s x w v + l j k = s u l r u w r 7 v h h v 2 q ' l h 7 h u p l q d w l r q 2 ' 7 w r q s d j h i r u h [ d f w u h t x l u h p h q w v 3. , i w k h 5 tt b 1 2 0 i h d w x u h z d v h q d e o h g l q w k h p r g h u h j l v w h u s u l r u w r h q w h u l q j s u h f k d u j h s r z h u g r z q p r g h w k h 2 ' 7 v l j q d o p x v w e h f r q w l q x r x v o \ u h j l v w h u h g / 2 : h q v x u l q j 5 tt l v l q d q r i i v w d w h , i the r tt b 1 2 0 i h d w x u h z d v g l v d e o h g l q w k h p r g h u h j l v w h u s u l r u w r h q w h u l q j s u h f k d u j h s r z h u g r z q p r g h 5 tt z l o o u h p d l q l q w k h r i i v w d w h 7 k h 2 ' 7 v l j q d o f d q e h u h j l v w h u h g h l w k h u / 2 : r u + , * + l q w k l v f d v h logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product ) r u e h w w h u v l j q d o l q w h j u l w \ ' ' 5 6 ' 5 $ 0 p h p r u \ v x e v \ v w h p g h v l j q v k d y h d g r s w h g x v h r i i o \ e \ w r s r o r j \ i r u w k h f r p p d q g v d g g u h v v h v f r q w u r o v l j q d o v d q g f o r f n v : 5 , 7 ( o h y h o l q j l v d v f k h p h i r u w k h p h p r u \ f r q w u r o o h u w r g h v n h z w k h ' 4 6 [ v w u r e h ' 4 6 [ ' 4 6 [ ? w r & . u h o d w l r q v k l s d w w k h 6 ' 5 $ 0 z l w k d v l p s o h i h h g e d f n i h d w x u h s u r y l g h g l w e \ w k h ' ' 5 6 ' 5 $ 0 l w v h o i : 5 , 7 ( o h y h o l q j l v j h q h u d o o \ x v h g d v s d u w r i w k h l q l w l d o l ] d w l r q s u r f h v v l i u h t x l u h g ) r u 1 2 5 0 $ / 6 ' 5 $ 0 r s h u d w l r q w k l v i h d w x u h p x v w e h g l v d e o h g 7 k l v l v w k h r q o \ 6 ' 5 $ 0 r s h u d w l r q z k h u h w k h ' 4 6 i x q f w l r q v d v d q l q s x w w r f d s w x u h w k h l q f r p l q j f o r f n d q g w k h ' 4 v i x q f w l r q d v r x w s x w v w r u h s r u w w k h v w d w r i w k h f o r f n 1 r w h w k d w q r q v w d q g d u g 2 ' 7 v f k h p h v d u h u h t x l u h g 7 k h p h p r u \ f r q w u r o o h u x v l q j w k h : 5 , 7 ( o h y h o l q j s u r f h g x u h p x v w k d y h d g m x v w d e o h g h o d \ v h w w l q j r q l w v ' 4 6 v w u r e h w r d o l j q w k h u l v l q j h g j h r i ' 4 6 w r w k h f o r f n d w w k h 6 ' 5 $ 0 s l q v 7 k l v l v d f f r p s o l v k h g z k h q w k h 6 ' 5 $ 0 d v \ q f k u r q r x v o \ i h h g v e d f n w k h & . v w d w x v y l d w k h ' 4 e x v d q g v d p s o h v z l w k w k h u l v l q j h g j h r i ' 4 6 7 k h f r q w u r o o h u u h s h d w h g o \ g h o d \ v w k h ' 4 6 v w u r e h x q w l o d & . w u d q v l w l r q i u r p v w w r v w l v g h w h f w h g 7 k h ' 4 6 g h o d \ h v w d e o l v k h g w k u r x j k w k l v s u r f h g x u h helps ensure t dqss, t dss, and t ' 6 + v s h f l i l f d w l r q v l q v \ v w h p v w k d w x v h i o \ e \ w r s r o r j \ e \ g h v n h z l q j w k h w u d f h o h q j w k p l v p d w f k $ f r q f h s w x d o w l p l q j r i w k l v s u r f h g x u h l v v k r z q l q ) l j x u h write leveling f igure 38- w rite l eveling c oncept ck ck# source differential dqs differential dqs differential dqs dq dq ck ck# destination destination push dqs to capture 0C1 transition t0 t1 t2 t3 t4 t5 t6 t7 t0 t1 t2 t3 t4 t5 t6 tn ck ck# t0 t1 t2 t3 t4 t5 t6 tn dont care 1 1 0 0 logic devices incorporated www.logicdevices.com 80 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product : k h q : 5 , 7 ( o h y h o l q j l v h q d e o h g w k h u l v l q j h g j h r i ' 4 6 v d p s o h v & . d q g w k h u l p h ' 4 r x w s x w v w k h v d p s o h g & . u v v w d w x v 7 k h s u l p h ' 4 i r u h d f k r i w k h z r u g v f r q w d l q h g l q w k h l 0 2 ' l v ' 4 i r u w k h o r z e \ w h ' 4 i r u w k h k l j k e \ w h , w r x w s x w v w k h v w d w x v r i & . v d p s o h g e \ / ' 4 6 [ d q g 8 ' 4 6 [ $ o o r w k h u ' 4 v ' 4 > @ ' 4 > @ i r u w k h o r z z r u g ' 4 > @ ' 4 > @ i r u w k h q h [ w z r u g ' 4 > @ ' 4 > @ i r u w k h q h [ w d q g ' 4 > @ ' 4 > @ i r u w k h + , * + z r u g f r q w l q x h w r g u l y h / 2 : 7 z r s u l p h ' 4 r q h d f k r i w k h z r u g v f r q w d l q h g l q w k h / ' , l 0 2 ' d o o r z h d f k e \ w h o d q h w r e h o h y h o h g l q g h s h q g h q w o \ write leveling $ p h p r u \ f r q w u r o o h u l q l w l d w h v w k h 6 ' 5 $ 0 : 5 , 7 ( / h y h o l q j p r g h e \ v h w w l q j w k h 0 5 > @ w r d v w d v v x p l q j w k h r w k h u s u r j u d p p d e o h i h d w x u h v 0 5 0 5 0 5 d q g 0 5 d u h i l u v w v h w d q g w k h ' / / l v i x o o \ u h v h w d q g o r f n h g 7 k h ' 4 e d o o v h q w h u w k h : 5 , 7 ( / h y h o l q j p r g h j r l q j i u r p d v + , * + = w v w d w h w r d q x q g h i l q h g g u l y - l q j v w d w h v r w k h ' 4 e x v v k r x o g q r w e h g u l y h q ' x u l q j : 5 , 7 ( / h y h o l q j p r g h r q o \ w k h 1 2 3 d q g ' ( 6 f r p p d q g v d u h d o o r z h g 7 k h p h p r u \ f r q w u r o o h u v k r x o g d w w h p s w w r o h y h o r q o \ r q h u d q n d w d w l p h w k x v w k h r x w s x w v r i r w k h u u d q n v v k r x o g e h g l v d e o h g e \ v h w w l q j 0 5 > @ w r d v w 7 k h p h p r u \ f r q w u r o o h u p d \ d v v h u w 2 ' 7 d i w h u d t 0 2 ' g h o d \ d v w k h 6 ' 5 $ 0 z l o o e h u h d g \ w r s u r f h v v w k h 2 ' 7 / r q g h o d \ : / t & . s u r y l g h g l w g r h v q r w y l r o d w h w k h d i r u h p h q w l r q h g t mod delay u h t x l u h p h q w 7 k h p h p r u \ f r q w u r o o h u p d \ g u l y h / ' 4 6 [ 8 ' 4 6 [ / 2 : d q g / ' 4 6 [ ? 8 ' 4 6 [ ? + , * + d i w h u t : / ' 4 6 ( 1 k d v e h h q v d w l v i l h g 7 k h f r q w u r o o h u p d \ e h j l q w r w r j j o h / ' 4 6 [ 8 ' 4 6 [ d i w h u t : / 0 5 ' r q h / > 8 @ ' 4 6 v w r j j o h l v ' 4 6 v w u d q v l w l r q l q j i u r p d / 2 : v w d w h w r d + , * + v w d w h z l w k / > 8 @ ' 4 6 [ ? w u d q v l w l r q l q j i u r p d + , * + v w d w h w r d / 2 : v w d w h w k h q e r w k w u d q v l w l r q e d f n w r w k h l u r u l j l q d o v w d w h v $ w d p l q l p x p 2 ' 7 / r q d q g t $ 2 1 p x v w e h v d w l v i l h g d w o h d v w r q h f o r f n s u l r u w r ' 4 6 w r j j o l q j $ i w h u t : / 0 5 ' d q g ' 4 6 / 2 : s u h d p e o h t : 3 5 ( k d y h e h h q v d w l v i l h g w k h p h p r u \ f r q w u r o o h u p d \ s u r y l g h h l w k h u d v l q j o h ' 4 6 [ w r j j o h r u p x o w l s o h ' 4 6 [ w r j j o h v w r v d p s o h & . i r u d j l y h q ' 4 6 [ w r & . v n h z ( d f k ' 4 6 w r j j o h p x v w q r w y l r o d w h t ' 4 6 / 0 , 1 d q g t ' 4 6 + 0 , 1 v s h f l i l f d w l r q v t ' 4 6 / 0 $ ; d q g t ' 4 6 + 0 $ ; v s h f l i l f d w l r q v d u h q r w d s s o l f d e o h g x u l q j : 5 , 7 ( o h y h o l q j p r g h 7 k h ' 4 6 [ p x v w e h d e o h w r g l v w l q j x l v k w k h & . u v u l v l q j h g j h z l w k l q t : / 6 d q g t : / + 7 k h s u l p h ' 4 z l o o r x w s x w w k h & . u v v w d w x v d v \ q f k u r q r x v o \ i u r p w k h d v v r f l d w h g ' 4 6 [ u l v l q j h g j h & . f d s w x u h z l w k l q t : / 2 7 k h u h p d l q l q j ' 4 v w k d w d o z d \ v g u l y h / 2 : z k h q ' 4 6 l v w r j j o l q j p x v w e h / 2 : z l w k l q t : / 2 ( d i w h u w k h i l u v w t : / 2 l v v d w l v i l h g w k h s u l p h ' 4 v j r l q j / 2 : $ v s u h y l r x v o \ q r w h g ' 4 6 [ l v d q l q s x w d q g q r w d q r x w s x w g x u l q j w k l v s u r f h v v ) l j x u h g h s l f w v w k h e d v l f w l p l q j s d u d p h w h u v i r u w k h r y h u d o o z u l w h o h y h o l q j s u r f h g x u h 7 k h p h p r u \ f r q w u r o o h u z l o o o l n h o \ v d p s o h h d f k d s s o l f d e o h s u l p h ' 4 v w d w h d q g g h w h u p l q h z k h w k h u w r l q f u h p h q w r u g h f u h p h q w l w ' 4 6 g h o d \ v h w w l q j $ i w h u w k h p h p r u \ f r q w u r o o h u s h u i r u p v h q r x j k ' 4 6 [ w r j j o h v w r g h w h f w w k h & . u v v w w u d q v l w l r q w k h p h p r u \ f r q w u r o o h u v k r x o g o r f n w k h ' 4 6 g h o d \ v h w w l q j i r u w k h 6 ' 5 $ 0 l 0 2 ' g h y l f h $ i w h u o r f n l q j w k h ' 4 6 v h w w l q j o h y h o l q j i r u w k h u d q n z l o o k d y h e h h q d f k l h y h g d q g w k h : 5 , 7 ( o h y h o l q j p r g h i r u w k h u d q n v k r x o g e h g l v d e o h g r u u h s u r j u d p p h g l i : 5 , 7 ( o h y h o l q j r i d q r w k h u u d q n i r o o r z v write leveling procedure logic devices incorporated www.logicdevices.com 81 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 39- w rite l eveling s equence ck ck# command t1 t2 early remaining dq late remaining dq t wloe nop 2 nop mrs 1 nop nop t wls t wlh dont care undefined driving mode indicates a break in time scale prime dq 5 differential dqs 4 odt t mod t dqsl 3 t dqs h 3 t dqsh 3 t wlo t wlmrd t wldqsen t wlo t wlo t wlo t dqsl 3 nop nop nop nop nop nop nop 1 2 7 ( 6 1. 0 5 6 / r d g 0 5 w r h q w h u z u l w h o h y h o l q j p r g h 2. 1 2 3 1 2 3 r u ' ( 6 3. ' 4 6 ' 4 6 q h h g v w r i x o i l o o p l q l p x p s x o v h z l g w k u h t x l u h p h q w v t ' 4 6 + 0 , 1 d q g t ' 4 6 / 0 , 1 d v g h i l q h g i r u u h j x o d u z u l w h v 7 k h p d [ l p x p s x o v h z l g w k l v v \ v w h p g h s h q g h q w 4. ' l i i h u h q w l d o ' 4 6 l v w k h g l i i h u h q w l d o g d w d v w u r e h ' 4 6 ' 4 6 7 l p l q j u h i h u h q f h s r l q w v d u h w k h ] h u r f u r v v l q j v 7 k h v r o l g o l q h u h s u h v h q w v ' 4 6 w k h g r w w h g o l q h u h s u h v h q w v ' 4 6 5. ' 5 $ 0 g u l y h v o h y h o l q j i h h g e d f n r q d s u l p h ' 4 ' 4 i r u [ d q g [ 7 k h u h p d l q l q j ' 4 d u h g u l y h q / 2 : d q g u h p d l q l q w k l v v w d w h w k u r x j k r x w w k h o h y h o l q j s u r f h g x u h $ i w h u w k h ' ' 5 6 ' 5 $ 0 l 0 2 ' k d v e h h q : 5 , 7 ( o h y h o h g w k h f r q w u r o o h u p x v w h [ l w i u r p : 5 , 7 ( / h y h o l q j p r g h e h i r u h w k h 1 2 5 0 $ / p r g h f d q e h x v h g ) l j x u h g h s l f w v d j h q h u d o s u r f h g x u h l q h [ l w l q j : 5 , 7 ( / h y h o l q j $ i w h u w k h o d v w u l v l q j ' 4 6 f d s w x u l q j d v w d w 7 w k h p h p r u \ f r q w u r o o h u v k r x o g v w r s g u l y l q j w k h ' 4 6 v l j q d o v d i w h u t : / 2 0 $ ; g h o d \ s o x v h q r x j k g h o d \ w r h q d e o h w k h p h p r u \ f r q w u r o o h u w r f d s w x u h w k h d s s o l f d e o h s u l p h ' 4 v w d w h d w y 7 e 7 k h ' 4 e d o o v e h f r p h x q g h i l q h g z k h q ' 4 6 q r o r q j h u u h p d l q v / 2 : d q g w k h \ u h p d l q x q g h i l q h g x q w l o t 0 2 ' d i w h u w k h 0 5 6 f r p p d q g d w 7 h 7 k h 2 ' 7 l q s x w v k r x o g e h g h d v v h u w h g / 2 : v x f k w k d w 2 ' 7 / r i i 0 , 1 h [ s l u h v d i w h u w k h ' 4 6 [ l v q r o r q j h u g u l y l q j / 2 : : k h q 2 ' 7 / 2 : v d w l v i l h v t is, odt p x v w e h n h s w / 2 : d w y 7 e x q w l o w k h 6 ' 5 $ 0 l v u h d g \ i r u h l w k h u d q r w k h u u d q n w r e h o h y h o h g r u x q w l o w k h 1 2 5 0 $ / p r g h f d q e h x v h g $ i w h u ' 4 6 w h u p l q d w l r q l v v z l w f k h g r i i : 5 , 7 ( o h y h o p r g h v k r x o g e h g l v d e o h g y l d w k h 0 5 6 f r p p d q g d w t $ $ i w h u t 0 2 ' l v v d w l v i l h g d w 7 h d q \ y d o l g f r p p d q g p d \ e h u h j l v w h u h g e \ w k h 6 ' 5 $ 0 6 r p h 0 5 6 f r p p d q g v p d \ e h l v v x h g d i w h u t 0 5 ' d w 7 g write leveling exit mode logic devices incorporated www.logicdevices.com 82 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 40- e xit w rite l eveling notes: 1. the dq result, = 1, between ta0 and tc0, is a result of the dqs, dqs# signals capturing ck high just after the t0 state. nop ck t0 t1 t2 ta0 tb0 tc0 tc1 tc2 td0 td1 te0 te1 ck# command odt r tt _dq nop r mponponponpon pon s nop nop add ress mr1 valid valid valid valid don t care transitioning r tt dqs, r tt dqs r # tt _ nom undefined driving mode t aof (max) t mrd indicates a break in time scale dqs, dqs# ck = 1 dq t is t aof (min) t mod t wlo + t wloe odtl off logic devices incorporated www.logicdevices.com 83 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product initialization 7 k h i r o o r z l q j v h t x h q f h l v u h t x l u h g i r u s r z h u x s d q g l q l w l d o l ] d w l r q d v v k r z q l q ) l j x u h 1. $ s s o \ s r z h u 5 ( 6 ( 7 ? l v u h f r p p h q g h g w r e h e h o r z [ 9 dd 4 g x u l q j s r z h u u d p s w r h q v x u h w k h r x w s x w v u h p d l q g l v d e o h g + , * + = d q g 2 ' 7 r i i 5 tt l v d o v r + , * + = $ o o r w k h u l q s x w v l q f o x g l q j 2 ' 7 p d \ e h x q g h i l q h g ' x u l q j s r z h u x s h l w k h u r i w k h i r o o r z l q j f r q g l w l r q v p d \ h [ l v w d q g p x v w e h p h w x condition a: x 9 dd d q g 9 dd 4 d u h g u l y h q i u r p d v l q j o h s r z h u v r x u f h d q g d u h u d p s h g z l w k d p d [ l p x p g h o w d y r o w d j h e h w z h h q w k h p r i ' 9 d p 9 6 o r s h u h y h u v d o r i d q \ s r z h u v x s s o \ v l j q d o l v d o o r z h g 7 k h y r o w d j h o h y h o v r q d o o e d o o v r w k h u w k d q 9 dd 9 dd 4 9 v v d q g 9 v v 4 p x v w e h o h v v w k d q r u h t x d o w r 9 dd 4 d q g 9 dd r q r q h v l g h d q g p x v w e h j u h d w h u w k d q r u h t x d o w r 9 v v 4 d q g 9 v v r q w k h r w k h u v l g h x % r w k 9 dd d q g 9 dd 4 s r z h u v x s s o l h v u d p s w r 9 dd 0 , 1 d q g 9 dd 4 0 , 1 z l w k l q t 9 dd 3 5 p v x % r w k 9 dd d q g 9 dd 4 s r z h u v x s s o l h v u d p s w r 9 dd 0 , 1 d q g 9 dd 4 0 , 1 z l w k l q t 9 dd 3 5 p v x 9 5 ( ) ' 4 w u d f n v 9 dd [ 9 5 ( ) & $ w u d f n v 9 dd x 0.5. x 9 tt l v o l p l w h g w r 9 z k h q w k h s r z h u u d p s l v f r p s o h w h d q g l v q r w d s s o l h g g l u h f w o \ w r w k h g h y l f h k r z h y h u t 9 7 ' v k r x o g e h j u h d w h u w k d q r u h t x d o w r ] h u r w r d y r l g g h y l f h o d w f k x s x & r q g l w l r q % x 9 dd p d \ e h d s s o l h g e h i r u h r u d w w k h v d p h w l p h d v 9 dd q. x 9 dd 4 p d \ e h d s s o l h g e h i r u h r u d w w k h v d p h w l p h d v 9 tt 9 5 ( ) ' 4 d q g 9 5 ( ) & $ . x 1 r v o r s h u h y h u v d o v d u h d o o r z h g l q w k h s r z h u v x s s o \ u d p s i r u w k l v f r q g l w l r q 2. 8 q w l o v w d e o h s r z h u p d l q w d l q 5 ( 6 ( 7 ? / 2 : w r h q v x u h w k h r x w s x w v u h p d l q g l v d e o h g + , * + = $ i w h u w k h s r z h u l v v w d e o h 5 ( 6 ( 7 ? p x v w e h / 2 : i r u d w o h d v w ? v w r e h j l q w k h l q l w l d o l ] d w l r q s u r f h v v 2 ' 7 z l o o u h p d l q l q w k h + , * + = v w d w h z k l o h 5 ( 6 ( 7 ? l v / 2 : d q g x q w l o & . ( l v u h j l v w h u h g + , * + 3. & . ( p x v w e h / 2 : q v s u l r u w r 5 ( 6 ( 7 ? w u d q v l w l r q l q j + , * + 4. $ i w h u 5 ( 6 ( 7 ? w u d q v l w l r q v + , * + z d l w ? v p l q x v r q h f o r f n z l w k & . ( / 2 : 5. $ i w h u w k l v & . ( / 2 : w l p h & . ( p d \ e h e u r x j k w + , * + v \ q f k u r q r x v o \ d q g r q o \ 1 2 3 r u ' ( 6 f r p p d q g v p d \ e h l v v x h g 7 k h f o r f n p x v w e h s u h v h q w d q g y d o l g i r u d w o h d v w q v d q g d p l q l p x p r i i l y h f o r f n v d q g 2 ' 7 p x v w e h g u l y h q / 2 : d w o h d v w w , 6 s u l r u w r & . ( e h l q j u h j l v w h u h g + , * + : k h q & . ( l v u h j l v w h u h g + , * + l w p x v w e h f r q w l q x r x v o \ u h j l v w h u h g + , * + x q w l o w k h i x o o l q l w l d o l ] d w l r q s u r f h v v l v f r p s o h w h 6. $ i w h u & . ( l v u h j l v w h u h g + , * + d q g d i w h u t ; 3 5 k d v e h h q v d w l v i l h g 0 5 6 f r p p d q g v p d \ e h l v v x h g , v v x h d q 0 5 6 / 2 $ ' 0 2 ' ( f r p p d q g w r 0 5 z l w k w k h d s s o l f d e o h v h w w l q j v s u r y l g h / 2 : w r % $ d q g % $ d q g + , * + w r % $ , v v x h d q 0 5 6 f r p p d q g w r 0 5 z l w k w k h d s s o l f d e o h v h w w l q j v 8. , v v x h d q 0 5 6 f r p p d q g w r 0 5 z l w k w k h d s s o l f d e o h v h w w l q j v l q f o x g l q j h q d e o l q j w k h ' / / d q g f r q i l j x u l q j 2 ' 7 9. , v v x h d q g 0 5 6 f r p p d q g w r 0 5 z l w k w k h d s s o l f d e o h v h w w l q j v l q f o x g l q j d ' / / 5 ( 6 ( 7 f r p p d q g t ' / / . f \ f o h v r i f o r f n l q s x w d u h u h t x l u h g w r o r f n w k h ' / / 10. , v v x h d = 4 & / f r p p d q g w r f d o l e u d w h 5 tt d q g 5 2 1 y d o x h v i r u w k h s u r f h v v y r o w d j h w h p s h u d w x u h 3 9 7 3 u l r u w r 1 2 5 0 $ / r s h u d w l r q t = 4 , 1 , 7 p x v w e h v d w l v i l h g 11. : k h q t dllk and t = 4 , 1 , 7 k d y h e h h q v d w l v i l h g w k h ' ' 5 6 ' 5 $ 0 z l o o e h u h d g \ i r u q r u p d o r s h u d w l r q operations logic devices incorporated www.logicdevices.com 84 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 41- i nitialization s equence ck e r tt ba[2:0] all voltage supplies valid and stable t = 200s (min) dm dqs add ress a10 ck ck# t cl command nop t0 ta0 don t care t cl t is t ck odt dq tb 0 t dllk mr1 with dll ena ble mr0 with dll reset t mrd t mod mrs mrs ba0 = h ba1 = l ba2 = l ba0 = l ba1 = l ba2 = l code code code code valid valid valid valid normal operation mr2 mr3 t mrd t mrd mrs mrs ba0 = l ba1 = h ba2 = l ba0 = h ba1 = h ba2 = l code code code code tc0 td 0 v tt v ref v dd q v dd reset# t = 500s (min) t ck s r x sta ble and vali d clo ck valid power-up ramp t (max) = 200ms dram ready for external commands t1 t zq init zq cali bration a10 = h zqcl t is see power-up c onditions in the initialization sequence text, set up 1 t xpr valid = 20ns t io z indicates a break in time scale t (min) = 10ns t vtd logic devices incorporated www.logicdevices.com 85 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 0 r g h u h j l v w h u v 0 5 0 5 d u h x v h g w r g h i l q h y d u l r x v p r g h v r i s u r j u d p p d e o h r s h u d w l r q r i w k h ' ' 5 6 ' 5 $ 0 l 0 2 ' $ p r g h u h j l v w h u l v s u r j u d p p h g y l d w k h 0 2 ' ( 5 ( * , 6 7 ( 5 6 ( 7 0 5 6 f r p p d q g g x u l q j l q l w l d o l ] d w l r q d q g l w u h w d l q v w k h v w r u h g l q i r u p d w l r q h [ f h s w i r u 0 5 > @ z k l f k l v v h o i f o h d u l q j x q w l o l w l v h l w k h u u h s u r j u d p p h g 5 ( 6 ( 7 ? j r h v / 2 : r u x q w l o w k h g h y l f h o r v h v s r z h u & r q w h q w v r i d p r g h u h j l v w h u f d q e h d o w h u h g e \ u h h [ h f x w l q j w k h 0 5 6 f r p p d q g , i w k h x v h u f k r r v h v w r p r g l i \ r q o \ d v x e v h w r i w k h p r g h u h j l v w h u u v y d u l d e o h v d o o y d u l d e o h v p x v w e h s u r j u d p p h g z k h q w k h 0 5 6 f r p p d q g l v l v v x h g 5 h s u r j u d p p l q j w k h p r g h u h j l v w h u z l o o q r w d o w h u w k h f r q w h q w v r i w k h p h p r u \ d u u d \ s u r y l g h g l w l v s h u i r u p h g f r u u h f w o \ 7 k h 0 5 6 f r p p d q g f d q r q o \ e h l v v x h g r u u h l v v x h g z k h q d o o e d q n v d u h l g o h d q g l q w k h 3 5 ( & + $ 5 * ( ' v w d w h t 5 3 l v v d w l v i l h g d q g q r g d w d e x u v w v d u h l q s u r j - u h v v $ i w h u d q 0 5 6 f r p p d q g k d v e h h q l v v x h g w z r s d u d p h w h u v p x v w e h v d w l v i l h g t mrd and t mod. 7 k h f r q w u r o o h u p x v w z d l w t 0 5 ' e h i r u h l q l w l d w l q j d q \ v x e v h t x h q w 0 5 6 f r p p d q g v v h h ) l j x u h mode registers f igure 42- mrs- to -mrs c ommand t iming ( t mrd) valid valid mrs 1 mrs 2 nop nop nop nop t0 t1 t2 ta0 ta1 ta2 ck# ck command add ress cke 3 don t care indicates a break in time scale t mrd 1 2 7 ( 6 1. 3 u l r u w r l v v x l q j w k h 0 5 6 f r p p d q g d o o e d q n v p x v w e h l g o h d q g s u h f k d u j h g t 5 3 0 , 1 p x v w e h v d w l v i l h g d q g q r g d w d e x u v w v f d q e h l q s u r j u h v v w k h o h y h o l q j s u r f h g x u h 2. t 0 5 ' v s h f l i l h v w k h 0 5 6 w r 0 5 6 f r p p d q g p l q l p x p f \ f o h w l p h 3. & . ( p x v w e h u h j l v w h u h g + , * + i u r p w k h 0 5 6 f r p p d q g x q w l o t 0 5 6 3 ' ( 1 0 , 1 v h h v 3 r z h u ' r z q 0 r g h w r q s d j h 4. ) r u d & $ 6 o d w h q f \ f k d q j h t ; 3 ' / / w l p l q j p x v w e h p h w e h i r u h d q \ q r q 0 5 6 f r p p d q g 7 k h f r q w u r o o h u p x v w d o v r z d l w t 0 2 ' e h i r u h l q l w l d w l q j d q \ q r q 0 5 6 f r p p d q g v h [ f o x g l q j 1 2 3 d q g ' ( 6 d v v k r z q l q ) l j x u h r q s d j h 7 k h ' 5 $ 0 u h t x l u h v t 0 2 ' l q r u g h u w r x s g d w h w k h u h t x h v w h g i h d w x u h v z l w k w k h h [ f h s w l r q r i ' / / 5 ( 6 ( 7 z k l f k u h t x l u h v d g g l w l r q d o w l p h 8 q w l o t 0 2 ' k d v e h h q v d w l v i l h g w k h x s g d w h g i h d w x u h v d u h w r e h d v v x p h g x q d y d l o d e o h logic devices incorporated www.logicdevices.com 86 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 43- mrs- to - non mrs c ommand t iming ( t mod) ck ck# command t1 t2 early remaining dq late remaining dq t wloe nop 2 nop mrs 1 nop nop t wls t wlh dont care undefined driving mode indicates a break in time scale prime dq 5 differential dqs 4 odt t mod t dqsl 3 t dqs h 3 t dqsh 3 t wlo t wlmrd t wldqsen t wlo t wlo t wlo t dqsl 3 nop nop nop nop nop nop nop 1 2 7 ( 6 1. 3 u l r u w r l v v x l q j w k h 0 5 6 f r p p d q g d o o e d q n v p x v w e h l g o h w k h \ p x v w e h s u h f k d u j h g t 5 3 p x v w e h v d w l v i l h g d q g q r g d w d e x u v w v f d q e h l q s u r j u h v v 2. 3 u l r u w r 7 d z k h q t 0 2 ' 0 , 1 l v e h l q j v d w l v i l h g q r f r p p d q g v h [ f h s w 1 2 3 ' ( 6 p d \ e h l v v x h g 3. , i 5 7 7 z d v s u h y l r x v o \ h q d e o h g 2 ' 7 p x v w e h u h j l v w h u h g / 2 : d w 7 v r w k d w 2 ' 7 / l v v d w l v i l h g s u l r u w r 7 d 2 ' 7 p x v w d o v r e h u h j l v w h u h g / 2 : d w h d f k u l v l q j & . h g j h i u r p 7 x q w l o t 0 2 ' 0 , 1 l v v d w l v i l h g d w 7 d 4. & . ( p x v w e h u h j l v w h u h g + , * + i u r p w k h 0 5 6 f r p p d q g x q w l o t 0 5 6 3 ' ( 1 0 , 1 d w z k l f k w l p h s r z h u g r z q p d \ r f f x u v h h v 3 r z h u ' r z q 0 r g h w r q s d j h mode register 0 (mr0) 7 k h e d v h u h j l v w h u 0 5 l v x v h g w r g h i l q h y d u l r x v ' ' 5 l 0 2 ' p r g h v r i r s h u d w l r q 7 k h v h g h i l q l w l r q v l q f o x g h w k h v h o h f w l r q r i d e x u v w o h q j w k e x u v w w \ s h & $ 6 o d w h q f \ r s h u d w l q j p r g h ' / / 5 ( 6 ( 7 : 5 , 7 ( u h f r y h u \ d q g 3 5 ( & + $ 5 * ( s r z h u g r z q p r g h d v v k r z q l q ) l j x u h logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product mode register 0 (mr0) $ f f h v v h v z l w k l q d j l y h q e x u v w p d \ e h s u r j u d p p h g w r h l w k h u d v h t x h q w l d o r u d q l q w h u o h d y h g r u g h u 7 k h e x u v w w \ s h l v v h o h f w h g y l d 0 5 > @ d v v k r z q l q ) l j x u h 7 k h r u g h u l q j r i d f f h v v h v z l w k l q d e x u v w l v g h w h u p l q h g e \ w k h e x u v w o h q j w k w k h e x u v w w \ s h d q g w k h v w d u w l q j f r o x p q d g g u h v v d v v k r z q l q 7 d e o h ' ' 5 r q o \ v x s s r u w v e l w e x u v w f k r s d q g e l w e x u v w d f f h v v p r g h v ) x o o l q w h u o h d y h g d g g u h v v r u g h u l q j l v v x s s r u w h g i r u 5 ( $ ' v z k l o h : 5 , 7 ( v d u h u h v w u l f w h g w r q l e e o h % & r u z r u g % / e r x q g d u l h v burst type burst length % x u v w o h q j w k l v g h i l q h g e \ 0 5 > @ v h h ) l j x u h 5 ( $ ' d q g : 5 , 7 ( d f f h v v h v w r w k h ' ' 5 6 ' 5 $ 0 l 0 2 ' d u h e x u v w r u l h q w h g z l w k w k h e x u v w o h q j w k e h l q j s u r j u d p p d e o h w r v w f k r s p r g h v w i l [ h g e x u v w r u v h o h f w - d e o h x v l q j $ g x u l q j d 5 ( $ ' : 5 , 7 ( f r p p d q g r q w k h i o \ 7 k h e x u v w o h q j w k g h w h u p l q h v w k h p d [ l p x p q x p e h u r i f r o x p q o r f d w l r q v w k d w f d q e h d f f h v v h g i r u d j l y h q 5 ( $ ' r u : 5 , 7 ( f r p p d q g : k h q 0 5 > @ l v v h w w r v w g x u l q j d 5 ( $ ' : 5 , 7 ( f r p p d q g l i $ w k h q % & f k r s p r g h l v v h o h f w h g , i $ w k h q % / p r g h l v v h o h f w h g 6 s h f l i l f w l p l q j g l d j u d p v d q g w x u q d u r x q g e h w z h h q 5 ( $ ' : 5 , 7 ( d u h v k r z q l q w k h 5 ( $ ' : 5 , 7 ( v h f w l r q v r i w k l v g r f x p h q w : k h q d 5 ( $ ' r u : 5 , 7 ( f r p p d q g l v l v v x h g d e o r f n r i f r o x p q v h t x d o w r w k h e x u v w o h q j w k l v h i i h f w l y h o \ v h o h f w h g $ o o d f f h v v h v i r u w k d w e x u v w w d n h s o d f h z l w k l q w k l v e o r f n p h d q l q j w k d w w k h e x u v w z l o o z u d s z l w k l q w k h e o r f n l i d e r x q g d u \ l v u h d f k h g 7 k h e o r f n l v x q l t x h o \ v h o h f w h g e \ $ > l @ z k h q w k h e x u v w o h q j w k l v v h w w r v w d q g e \ $ > l @ z k h q w k h e x u v w o h q j w k l v v h w w r v w z k h u h $ l l v w k h p r v w v l j q l i l f d q w f r o x p q d g g u h v v e l w i r u d j l y h q v w d u w l q j o r f d - w l r q z l w k l q w k h e o r f n 7 k h s u r j u d p p h g e x u v w o h q j w k d s s o l h v w r e r w k 5 ( $ ' d q g : 5 , 7 ( e x u v w v f igure 44- m ode r egister 0 (mr0) d efinitions notes: 1. mr0[16, 13, 7, 2] are reserved for future use and must be programmed to 0. 0 1 bl cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 0 (mr0) address bus 9765432 810 a10 a12 a11 1a b0 ab 3 12 11 10 1 m3 0 1 read burst type sequential (nibble) interleaved cas latency reserved 5 6 7 8 9 10 11 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 15 dll write recovery reserved 5 6 7 8 10 12 reserved wr 0 0 m12 0 1 precharge pd dll off (slow exit) dll on (fast exit) ba2 16 0 1 burst length fixed bl8 4 or 8 (on-the-fly via a12) fixed bc4 (chop) reserved m0 0 1 0 1 m1 0 0 1 1 m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 m14 0 1 0 1 m15 0 0 1 1 mode register mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) mode register 3 (mr3) a13 14 0 1 0 1 m8 0 1 dll reset no yes logic devices incorporated www.logicdevices.com 88 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product burst length read/write address (a[2,1,0]) type = sequential type = interleaved & + 2 3 8 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = ; ; ; ; ; ; ; ; t able 60: b urst o rder notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,3,4 1,3,4 1 1 1 1 1 1 1 1 1,3 burst type (decimal) = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = ; ; ; ; ; ; ; ; 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 9 9 9 9 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 9 9 9 5 ( $ ' : 5 , 7 ( 5 ( $ ' : 5 , 7 ( starting column 2. = ' d w d d q g 6 w u r e h r x w s x w g u l y h u v l q w u l v w d w h 3. ; w ' r q u w & d u h w 1 2 7 ( 6 1. , q w h u q d o 5 ( $ ' d q g : 5 , 7 ( r s h u d w l r q v v w d u w d w w k h v d p h s r l q w l q w l p h i r u % & d v w k h \ g r i r u % / ' / / 5 ( 6 ( 7 l v g h i l q h g e \ 0 5 > @ v h h ) l j x u h 3 u r j u d p p l q j 0 5 > @ w r v w d f w l y d w h v w k h ' / / 5 ( 6 ( 7 i x q f w l r q 0 5 > @ l v v h o i f o h d u l q j p h d q - l q j l w u h w x u q v w r d y d o x h r i v w d i w h u w k h ' / / 5 ( 6 ( 7 i x q f w l r q k d v e h h q initiated. $ q \ w l p h w k h ' / / 5 ( 6 ( 7 i x q f w l r q k d v e h h q l q l w l d w h g & . ( p x v w e h + , * + d q g w k h f o r f n k h o g v w d e o h i r u t ' / / . f o r f n f \ f o h v e h i r u h d 5 ( $ ' f r p p d q g f d q e h l v v x h g 7 k l v l v w r d o o r z w l p h i r u w k h l q w h u q d o f o r f n w r e h v \ q f k u r q l ] h g z l w k w k h h [ w h u q d o f o r f n ) d l o l q j w r z d l w i r u v \ q f k u r q l ] d w l r q w r r f f x u p d \ u h v x o w l q l q y d o l g r x w s x w w l p l q j v s h f l i l f d w l r q v v x f k d v t ' 4 6 & . w l p l q j v dll reset : 5 , 7 ( 5 ( & 2 9 ( 5 < w l p h l v g h i l q h g e \ 0 5 > @ v h h ) l j x u h : 5 , 7 ( 5 ( & 2 9 ( 5 < y d o x h v r i r u p d \ e h x v h g e \ s u r j u d p p l q j 0 5 > @ 7 k h x v h u l v u h t x l u h g w r s u r j u d p w k h f r u u h f w y d o x h r i : 5 , 7 ( 5 ( & 2 9 ( 5 < d q g l v f d o f x o d w h g e \ g l y l g l q j t : 5 q v e \ t & . q v d q g u r x q g - l q j x s d q r q l q w h j h u y d o x h w r w k h q h [ w l q w h j h u : 5 f \ f o h v u r x q g x s t : 5 > q v @ t & . > q v @ write recovery logic devices incorporated www.logicdevices.com 89 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 7 k h 3 5 ( & + $ 5 * ( 3 ' e l w d s s o l h v r q o \ z k h q 3 5 ( & + $ 5 * ( s r z h u g r z q p r g h l v e h l q j x v h g : k h q 0 5 > @ l v v h w w r v w w k h ' / / l v r i i g x u l q j 3 5 ( & + $ 5 * ( s r z h u g r z q s u r y l g l q j d o r z h u v w d q g e \ f x u u h q w p r g h k r z- ever, t ; 3 ' / / p x v w e h v d w l v i l h g z k h q h [ l w l q j : k h q 0 5 > @ l v v h w w r v w w k h ' / / f r q w l q x h v w r u x q g x u l q j 3 5 ( & + $ 5 * ( s r z h u g r z q p r g h w r h q d e o h d i d v w h u h [ l w r i 3 5 ( & + $ 5 * ( s r z h u g r z q p r g h k r z h y h u t ; 3 p x v w e h v d w l v i l h g z k h q h [ l w l q j v h h 3 r z h u ' r z q p r g h r q 3 d j h precharge power-down (precharge pd) 7 k h & / l v g h i l q h g e \ 0 5 > @ d v v k r z q l q ) l j x u h & $ 6 o d w h q f \ l v w k h g h o d \ d v p h d v x u h g l q f o r f n f \ f o h v e h w z h h q w k h l q w h u q d o 5 ( $ ' f r p p d q g d q g w k h d y d l o d e l o l w \ r i w k h i l u v w e l w r i y d o l g r x w s x w g d w d 7 k h & / f d q e h v h w w r r u ' ' 5 6 ' 5 $ 0 l 0 2 ' v g r q r w v x s s r u w k d o i f o r f n o d w h q f l h v ( [ d p s o h v r i & / d q g & / d u h v k r z q l q ) l j x u h e h o r z , i d q l q w h u q d o 5 ( $ ' f r p p d q g l v u h j l v w h u h g d w f o r f n h g j h q d q g w k h & $ 6 o d w h q f \ l v p f o r f n v w k h g d w d z l o o e h d y d l o d e o h q r p l q d o o \ f r l q f l g h q w z l w k f o r f n h g j h q p 7 d e o h l q g l f d w h v w k h & / v v x s s r u w h g d w d y d l o d e o h r s h u d w l q j i u h t x h q f l h v cas latency (cl) f igure 45- read l atency read nop nop nop nop nop nop nop ck ck# command dq dqs, dqs# dqs, dqs# t0 t1 t2 t3 t4 t5 t6 t7 t8 dont care ck ck# command dq read nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 di n + 3 di n+ 1 di n + 2 di n + 4 di n di n nop nop al = 0, cl = 8 al = 0, cl = 6 transitioning data 1 2 7 ( 6 1. ) r u l o o x v w u d w l r q s x u s r v h v r q o \ & / d q g & / d u h v k r z q 2 w k h u & / y d o x h v d u h s r v v l e o h 2. 6 k r z q z l w k q r p l q d o t ' 4 6 & . d q g q r p l q d o t dsdq. logic devices incorporated www.logicdevices.com 90 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 7 k h 0 2 ' ( 5 ( * , 6 7 ( 5 0 5 f r q w u r o v d g g l w l r q d o i x q f w l r q v d q g i h d w x u h v q r w d y d l o d e o h l q w k h r w k h u p r g h u h j l v w h u v 4 2 ) ) 2 8 7 3 8 7 ' , 6 $ % / ( ' / / ( 1 $ % / ( ' / / ' , 6 $ % / ( 5 tt b 1 2 0 y d o x h 2 ' 7 : 5 , 7 ( / ( 9 ( / , 1 * 3 2 6 7 ( ' & $ 6 $ ' ' , 7 , 9 ( o d w h q f \ d q g 2 8 7 3 8 7 ' 5 , 9 ( 6 7 5 ( 1 * 7 + 7 k h v h i x q f w l r q v d u h f r q w u r o o h g y l d w k h e l w v v k r z q l q ) l j x u h e h o r z 7 k h 0 5 u h j l v w h u l v s u r j u d p p h g y l d w k h 0 5 f r p p d q g d q g u h w d l q v w k h v w r u h g l q i r u p d w l r q x q w l o l w l v u h s u r j u d p p h g x q w l o 5 ( 6 ( 7 ? j r h v / 2 : w u x h r u x q w l o w k h g h y l f h o r v h v s r z h u 5 h s u r j u d p p l q j w k h 0 5 u h j l v w h u z l o o q r w d o w h u w k h f r q w h q w v r i w k h p h p r u \ d u u d \ s u r y l g h g w k h r s h u d w l r q l v s h u i r u p h g f r u u h f w o \ 7 k h 0 5 u h j l v w h u p x v w e h o r d g h g z k h q d o o e d q n v d u h l g o h d q g q r e x u v w v d u h l q s u r j u h v v 7 k h f r q w u r o o h u p x v w v d w l v i \ w k h v s h f l i l h g w l p l q j s d u d p h w h u v t mrd and t 0 2 ' e h i r u h l q l w l d w l q j d v x e v h t x h q w r s h u d w l r q mode register 1 (mr1) f igure 46- m ode r egister 1 (mr1) d efinition al r tt q off a9 a7 a6 a5 a4 a3 2a 8 aa1 a0 mode register 1 (mr1) address bus 9 7 6 5 4 3 2 810 a10 a12 a11 1ab 0ab 31 21 11 01 m0 0 1 dll enable enable (normal) disable m5 0 0 1 1 output drive strength rzq/6 (40 [nom]) rzq/7 (34 [nom]) reserved reserved 14 wl 1 sdo 0 dll r tt tdqs m12 0 1 q off enabled disabled ba2 15 0 1 m7 0 1 write levelization disable (normal) enable additive latency (al) disabled (al = 0) al = cl - 1 al = cl - 2 reserved m3 0 1 0 1 m4 0 0 1 1 r tt ods m1 0 1 0 1 a13 16 0 1 m11 0 1 tdqs disabled enabled 0 1 0 1 r tt _ nom (odt) 2 non-writes r tt _ nom disabled rzq/4 (60 [nom]) rzq/2 (120 [nom]) rzq/6 (40 [nom]) rzq/12 (20 [nom]) rzq/8 (30 [nom]) reserved reserved r tt _ nom (odt) 3 writes r tt _ nom disabled rzq/4 (60 [nom]) rzq/2 (120 [nom]) rzq/6 (40 [nom]) n/a n/a reserved reserved m2 0 1 0 1 0 1 0 1 m6 0 0 1 1 0 0 1 1 m9 0 0 0 0 1 1 1 1 mode register mode register set 0 (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) m14 0 1 0 1 m15 0 0 1 1 1 2 7 ( 6 1. 0 5 > @ d u h u h v h u y h g i r u i x w x u h x v h d q g p x v w e h s u r j u d p p h g w r v w 2. ' x u l q j z u l w h o h y h o l q j l i 0 5 > @ d q g 0 5 > @ d u h v w w k h q d o o 5 tt b 1 2 0 y d o x h v d u h d y d l o d e o h i r u x v h 3. ' x u l q j z u l w h o h y h o l q j l i 0 5 > @ l v d v w e x w 0 5 > @ l v d v w w k h q r q o \ 5 tt b 1 2 0 z u l w h y d o x h v d u h d y d l o d e o h i r u x v h logic devices incorporated www.logicdevices.com 91 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 7 k h ' / / p d \ e h h q d e o h g r u g l v d e o h g e \ s u r j u d p p l q j 0 5 > @ g x u l q j w k h / 2 $ ' 0 2 ' ( f r p p d q g d v v k r z q l q ) l j x u h s u h y l r x v s d j h 7 k h ' / / p x v w e h h q d e o h g i r u 1 2 5 0 $ / r s h u d w l r q ' / / ( 1 $ % / ( l v u h t x l u h g g x u l q j s r z h u x s l q l w l d o l ] d w l r q d q g x s r q u h w x u q l q j w r 1 2 5 0 $ / r s h u d w l r q d i w h u k d y l q j ' , 6 $ % / ( ' w k h ' / / i r u w k h s x u s r v h r i g h e x j j l q j r u h y d o x d - w l r q ( 1 $ % / , 1 * w k h ' / / v k r x o g d o z d \ v e h i r o o r z h g e \ u h v h w w l q j w k h ' / / x v l q j w k h d s s u r s u l d w h / 2 $ ' 0 2 ' ( f r p p d q g , i w k h ' / / l v h q d e o h g s u l r u w r h q w h u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h w k h ' / / l v d x w r p d w l f d o o \ ' , 6 $ % / ( ' z k h q h q w h u l q j 6 ( / ) 5 ( ) 5 ( 6 + r s h u d w l r q d q g l v d x w r p d w l f d o o \ 5 ( ( 1 $ % / ( ' d q g 5 ( 6 ( 7 x s r q h [ l w r i 6 ( / ) 5 ( ) 5 ( 6 + , i w k h ' / / l v ' , 6 $ % / ( ' s u l r u w r h q w h u l q j 6 ( / ) 5 ( ) 5 ( 6 + w k h ' / / u h p d l q v ' , 6 $ % / ( ' h y h q x s r q h [ l w r i w k h 6 ( / ) 5 ( ) 5 ( 6 + r s h u d w l r q x q w l o l w k d v e h h q 5 ( ( 1 $ % / ( ' d q g 5 ( 6 ( 7 7 k h 6 ' 5 $ 0 l v q r w w h v w h g q r u g r h v / ' , z d u u d q w f r p s o l d q f h z l w k 1 2 5 0 $ / p r g h w l p l q j v r u i x q f w l r q d o l w \ z k h q w k h ' / / l v g l v d e o h g $ q d w w h p s w k d v e h h q p d g h i r u w k h 6 ' 5 $ 0 w r r s h u d w h l q w k h 1 2 5 0 $ / p r g h z k h q h y h u s r v v l e o h z k h q w k h ' / / l v g l v d e o h g k r z h y h u e \ l q g x v w u \ v w d q g d u g v w k h i r o o r z l q j h [ f h s w l r q v k d y h e h h q r e v h u y h g g h i l q h g d q g o l v w h g 1. 2 ' 7 l v 1 2 7 $ / / 2 : ( ' w r e h x v h g 2. 7 k h 2 8 7 3 8 7 ' $ 7 $ l v q r o r q j h u h g j h d o l j q h g w r w k h f o r f n 3. & / d q g & : / f d q r q o \ e h v l [ f o r f n v : k h q w k h ' / / l v ' , 6 $ % / ( ' w l p l q j d q g i x q f w l r q d o l w \ f d q y d u \ i u r p w k h 1 2 5 0 $ / r s h u d w l r q d o v s h f l i l f d w l r q v z k h q w k h ' / / l v h q d e o h g ' , 6 - $ % / , 1 * w k h ' / / d o v r l p s o l h v w k h q h h g w r f k d q j h w k h f o r f n i u h t x h q f \ dll enable/dll disable 2 ' 7 u h v l v w d q f h 5 tt b 1 2 0 l v g h i l q h g e \ 0 5 > @ v h h ) l j x u h 7 k h r tt w h u p l q d w l r q y d o x h d s s o l h v w r w k h ' 4 [ / ' 0 [ 8 ' 0 [ / > 8 @ ' 4 6 [ d q g / > 8 @ ' 4 6 [ ? 7 k h ' ' 5 g h y l f h d u f k l w h f w x u h v x s s r u w v p x o w l s o h 5 tt w h u p l q d - w l r q y d o x h v e d v h g r q 5 = 4 q z k h u h q f d q e h r u d q g 5 = 4 l v :. 8 q o l n h ' ' 5 ' ' 5 2 ' 7 p x v w e h w x u q h g r i i s u l r u w r 5 ( $ ' , 1 * g d w d r x w d q g p x v w u h p d l q r i i g x u l q j 5 ( $ ' e x u v w 5 tt b 1 2 0 w h u p l q d w l r q l v d o o r z h g d q \ w l p h d i w h u w k h ' 5 $ 0 l v l q l w l d o l ] h g f d o l e u d w h g d q g q r w s h u i r u p l q j 5 ( $ ' d f f h v v h v r u l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h $ g g l w l r q d o o \ : 5 , 7 ( d f f h v v h v z l w k g \ q d p l f 2 ' 7 h q d e o h g 5 tt b : 5 w h p s r u d u l o \ u h s o d f h v 5 tt b 1 2 0 z l w k r tt b : 5 7 k h d f w x d o h i i h f w l y h w h u p l q d w l r q 5 tt b ( ) ) p d \ e h g l i i h u h q w i u r p w k h 5 tt w d u j h w h g y d o x h g x h w r q r q o l q h d u l w \ r i w k h w h u p l q d w l r q ) r u 5 tt b ( ) ) y d o x h v d q g f d o f x o d w l r q v v h h w k h 2 1 ' , ( 7 ( 5 0 , 1 $ 7 , 2 1 2 ' 7 g h v f u l s w l r q o d w h u in this ds. 7 k h 2 ' 7 i h d w x u h l v g h v l j q h g w r l p s u r y h v l j q d o l q w h j u l w \ r i w k h p h p r u \ g h y l f h e \ h q d e o l q j w k h ' ' 5 6 ' 5 $ 0 f r q w u r o o h u w r l q g h s h q g h q w o \ w x u q 2 1 2 ) ) 2 ' 7 i r u d q \ r u d o o g h y l f h v l q w k h h q g g h v l j q v d u u d \ 7 k h 2 ' 7 l q s x w f r q w u r o s l q l v x v h g w r g h w h u p l q h z k h q 5 tt l v w x u q h g r q 2 ' 7 / r q d q g r i i 2 ' 7 / r i i d v v x p l q j 2 ' 7 k d v e h h q ( 1 $ % / ( ' y l d 0 5 > @ 7 l p l q j v i r u 2 ' 7 d u h g h w d l o h g l q w k h v 2 1 ' , ( 7 h u p l q d w l r q 2 ' 7 w g h v f u l s - tion later in this ds. on-die termination (odt) 7 k h ' ' 5 6 ' 5 $ 0 l 0 2 ' x v h v d s u r j u d p p d e o h l p s h g d q f h r x w s x w e x i i h u 7 k h g u l y h v w u h q j w k p r g h u h j l v w h u v h w w l q j l v g h i l q h g e \ 0 5 > @ 5 = 4 : > 1 2 0 @ l v w k h s u l p d u \ r x w s x w g u l y h u l p s h g d q f h v h w w l q j i r u w k h g h y l f h 7 r f d o l e u d w h w k h r x w s x w g u l y h u l p s h g d q f h d q g h [ w h u q d o s u h f l v l r q u h v l v w r u 5 = 4 l v f r q q h f w h g e h w z h h q w k h = 4 e d o o d q g 9 v v 4 7 k h y d o x h r i the resistor is 240 : ? 7 k h r x w s x w l p s h g d q f h l v v h w g x u l q j l q l w l d o l ] d w l r q $ g g l w l r q d o l p s h g d q f h f d o l e u d w l r q x s g d w h v g r q r w d i i h f w g h y l f h r s h u d w l r q d q g d o o g d w d v k h h w w l p - l q j v d q g f x u u h q w v s h f l i l f d w l r q v d u h p h w g x u l q j d q x s g d w h 7 r p h h w w k h : v s h f l i l f d w l r q w k h r x w s x w g u l y h v w u h q j w k p x v w e h v h w w r 34 : g x u l q j l q l w l d o l ] d w l r q 7 r r e w d l q d f d o l e u d w h g r x w s x w g u l y h u l p s h g d q f h d i w h u s r z h u x s w k h ' ' 5 l 0 2 ' 6 ' 5 $ 0 q h h g v d f d o l e u d w l r q f r p p d q g w k d w l v s d u w r i w k h l q l w l d o l ] d w l r q d q g u h v h w s u r f h g x u h output drive strength 7 k h 2 8 7 3 8 7 ( 1 $ % / ( i x q f w l r q l v g h i l q h g e \ 0 5 > @ d v v k r z q l q ) l j x u h : k h q h q d e o h g 0 5 > @ d o o r x w s x w v ' 4 [ ' 4 6 [ ' 4 6 [ ? d u h w u l v w d w h g 7 k h r x w s x w ' , 6 $ % / ( i h d w x u h l v l q w h q g h g w r e h x v h g g x u l q j i dd f k d u d f w h u l ] d w l r q r i w k h 5 ( $ ' f x u u h q w d q g g x u l q j t ' 4 6 6 p d u j l q l q j : 5 , 7 ( / ( 9 ( / , 1 * r q o \ output enable/disable 7 k h : 5 , 7 ( / ( 9 ( / , 1 * i x q f w l r q l v h q d e o h g e \ 0 5 > @ d v v k r z q l q ) l j x u h : 5 , 7 ( / ( 9 ( / , 1 * l v x v h g g x u l q j l q l w l d o l ] d w l r q w r g h v n h z w k h ' 4 6 [ v w u r e h w r f o r f n r i i v h w d v d u h v x o w r i i o \ e \ w r s r o r j \ g h v l j q v ) r u e h w w h u v l j q d o l q w h j u l w \ v r p h h q g x v h g h v l j q v r i ' ' 5 g h y l f h v d g r s w h g i o \ e \ w r s r o r j \ i r u w k h f r p p d q g v d g g u h v v h v f r q w u r o v l j q d o v d q g f o r f n v 7 k h i o \ e \ w r s r o r j \ e h q h i l w v i u r p d u h g x f h g q x p e h u r i v w x e v d q g w k h l u o h q j w k v k r z h y h u i o \ e \ w r s r o r j \ l q g x f h v i o l j k w w l p h v n h z e h w z h h q w k h f o r f n d q g ' 4 6 [ v w u r e h d q g ' 4 [ d w h d f k 6 ' 5 $ 0 l q w k h d u u d \ & r q w u r o - o h u v z l o o k d y h d g l i i l f x o w w l p h p d l q w d l q l q j t dqss, t dss and t ' 6 + v s h f l i l f d - w l r q v z l w k r x w v x s s r u w l q j : 5 , 7 ( / ( 9 ( / , 1 * l q v \ v w h p v z k l f k x v h i o \ e \ w r s r o r j \ e d v h g g h v l j q v : 5 , 7 ( / ( 9 ( / , 1 * w l p l q j d q g g h w d l o h g r s h u d w l r q l q i r u p d w l r q l v s u r y l g h g l q v : 5 , 7 ( / ( 9 ( / , 1 * write leveling logic devices incorporated www.logicdevices.com 92 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product $ / l v v x s s r u w h g w r p d n h w k h f r p p d q g d q g g d w d e x v h i i l f l h q w i r u v x v w d l q d e o h e d q g z l g w k v l q ' ' 5 6 5 $ 0 v 0 5 > @ g h i l q h w k h y d o x h r i $ / v h h ) l j x u h 0 5 > @ h q d e o h v w k h x v h u w r s u r j u d p w k h ' ' 5 6 ' 5 $ 0 z l w k d q $ / & / r u & / : l w k w k l v i h d w x u h w k h ' ' 5 6 ' 5 $ 0 h q d e o h v d 5 ( $ ' r u : 5 , 7 ( f r p p d q g w r e h l v v x h g d i w h u w k h $ & 7 , 9 $ 7 ( f r p p d q g i r u w k d w e d q n s u l r u w r t 5 & ' 0 , 1 7 k h r q o \ u h v w u l f w l r q l v $ & 7 , 9 $ 7 ( w r 5 ( $ ' r u : 5 , 7 ( $ / t t 5 & ' 0 , 1 p x v w e h v d w l v i l h g $ v v x p l q j t 5 & ' 0 , 1 & / d w \ s l f d o d s s o l f d w l r q x v l q j w k l v i h d w x u h v h w v $ / & / y t & . t 5 & ' 0 , 1 t & . 7 k h 5 ( $ ' r u : 5 , 7 ( f r p p d q g l v k h o g i r u w k h w l p h r i w k h $ / e h i r u h l w l v u h o h d v h g l q w h u q d o o \ w r w k h ' ' 5 6 ' 5 $ 0 l 0 2 ' g h y l f h 5 ( $ ' o d w h q f \ 5 / l v f r q w u r o o h g e \ w k h v x p r i w k h $ / d q g & $ 6 o d w h q f \ & / 5 / $ / & / : 5 , 7 ( o d w h q f \ : / l v w k h v x p r i & $ 6 : 5 , 7 ( o d w h q f \ d q g $ / : / $ / & : / v h h v 0 2 ' ( 5 ( * , 6 7 ( 5 0 5 w ( [ d p s o h v r i 5 ( $ ' d q g : 5 , 7 ( o d w h q f l h v d u h v k r z q l q ) l j x u h d q g ) l j x u h posted cas additive latency (al) f igure 47- read l atency (al = 5, cl = 6) ck ck# command dq dqs, dqs# active n t0 t1 dont care nop nop t6 t12 nop read n t13 nop do n+ 3 do n + 2 do n + 1 rl = al + cl = 11 t14 nop do n t rcd (min) al = 5 cl = 6 t11 bc4 indicates a break in time scale transitioning data t2 nop logic devices incorporated www.logicdevices.com 93 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 48- m ode r egister 2 (mr2) d efinition notes: 1. mr2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. m14 0 1 0 1 m15 0 0 1 1 mode register mode register set 0 (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mode register 2 (mr2) add ress bus 976543 8210 a10 a12 a11 1a b0 ab 10 11 121314 15 1 cw l 0 1 0 ba2 as r 16 0 1 a13 0 1 0 1 0 1 0 1 0 1 0 1 srt r tt _ wr m6 0 1 auto self refres h (optional) disabled: manual enabled: automatic m7 0 1 self refresh temperature normal (0 c to 85 c) extended (0c to 95 c) cas write latency (cwl) 5 ck ( t ck 2.5ns) 6 ck (2.5ns > t ck 1.875ns) 7 ck (1.875ns > t ck 1.5ns) 8 ck (1.5ns > t ck 1.25ns) reserved reserved reserved reserved m3 0 1 0 1 0 1 0 1 m4 0 0 1 1 0 0 1 1 m5 0 0 0 0 1 1 1 1 m9 0 1 0 1 m10 0 0 1 1 dynamic odt ( r tt _ wr ) r tt _ wr disabled rzq/4 rzq/2 reserved 7 k h 0 2 ' ( 5 ( * , 6 7 ( 5 0 5 f r q w u r o v d g g l w l r q d o i x q f w l r q v d q g i h d w x u h v q r w d y d l o d e o h l q w k h r w k h u p r g h u h j l v w h u v 7 k h v h d g g l w l r q d o i x q f w l r q v d u h & $ 6 : 5 , 7 ( o d w h q f \ & : / $ 8 7 2 6 ( / ) 5 ( ) 5 ( 6 + $ 6 5 6 ( / ) 5 ( ) 5 ( 6 + 7 ( 0 3 ( 5 $ 7 8 5 ( 6 5 7 d q g ' < 1 $ 0 , & 2 ' 7 5 tt b : 5 7 k h v h i x q f w l r q v d u h f r q - w u r o o h g y l d w k h e l w v v k r z q l q ) l j x u h 7 k h 0 5 l v s u r j u d p p h g y l d w k h 0 5 6 f r p p d q g d q g z l o o u h w d l q w k h v w r u h g l q i r u p d w l r q x q w l o l w l v s u r j u d p p h g d j d l q r u x q w l o w k h g h y l f h o r v h v s r z h u 5 h s u r j u d p p l q j w k h 0 5 u h j l v w h u z l o o q r w d o w h u w k h f r q w h q w v r i w k h p h p r u \ d u u d \ s u r y l g h g w k d w w k h r s h u d w l r q k d v e h h q s h u i r u p h g f r u u h f w o \ 7 k h 0 5 u h j l v w h u p x v w e h o r d g h g z k h q d o o e d q n v d u h l g o h d q g q r g d w d e x u v w v d u h l q s u r j u h v v d q g w k h p h p r u \ f r q w u r o o h u p x v w z d l w i r u w k h v s h f l i l h g w l p h t mrd and t 0 2 ' e h i r u h l q l w l d w l q j d v x e v h t x h q w r s h u d w l r q mode register 2 (mr2) logic devices incorporated www.logicdevices.com 94 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 49- cas w rite l atency ck ck# command dq dqs, dqs# active n bc4 t0 t1 dont care nop nop t6 t12 nop write n t13 nop di n + 3 di n + 2 di n + 1 t14 nop di n t rcd (min) nop al = 5 t11 indicates a break in time scale wl = al + cwl = 11 transitioning data t2 cwl = 6 & : / l v g h i l q h g e \ 0 5 > @ d q g l v w k h g h o d \ l q f o r f n f \ f o h v i u r p w k h u h o h d v l q j r i w k h l q w h u q d o : 5 , 7 ( w r w k h o d w f k l q j r i w k h i l u v w g d w d l q & : / p x v w e h f r u u h f w o \ v h w w r w k h f r u u h v s r q g l q j r s h u d w l q j f o r f n i u h t x h q f \ v h h ) l j x u h 7 k h r y h u d o o : 5 , 7 ( / $ 7 ( 1 & < : / l v h t x d o w r & : / $ / v h h ) l j x u h cas write latency (cwl) 0 r g h u h j l v w h u 0 5 > @ l v x v h g w r ' , 6 $ % / ( ( 1 $ % / ( w k h $ 6 5 i x q f w l r q : k h q $ 6 5 l v ' , 6 $ % / ( ' w k h 6 ( / ) 5 ( ) 5 ( 6 + p r g h u v 5 ( ) 5 ( 6 + u d w h l v d v v x p h g w r e h d w w k h q r u p d o ? & o l p l w f r p p r q o \ u h i h u u h g w r d v w k h ; 5 ( ) 5 ( 6 + u d w h , q w k h ' , 6 $ % / ( ' p r g h $ 6 5 u h t x l u h v w k h x v h u w r h q v x u h w k h 6 ' 5 $ 0 q h y h u h [ f h h g v d 7 $ r i ? & z k l o h l q 6 ( / ) 5 ( ) 5 ( 6 + x q o h v v w k h x v h u h q d e o h v w k h 6 5 7 i h d w x u h o l v w h g e h o r z v x s s r u w l q j d q h o h - y d w h g w h p s x s w r ? & z k l o h l q 6 ( / ) 5 ( ) 5 ( 6 + 7 k h v w d q g d u g 6 ( / ) 5 ( ) 5 ( 6 + f x u u h q w w h v w v s h f l i l h v w h v w f r q g l w l r q v w r q r u p d o d p e l h q w w h p s h u d w x u h ? & r q o \ p h d q l q j l i $ 6 5 l v h q d e o h g w k h v w d q g d u g 6 ( / ) 5 ( ) 5 ( 6 + f x u u h q w v s h f l i l f d w l r q g r h v q r w d s s o \ v h h w k h v ( ; 7 ( 1 ' ( ' 7 ( 0 3 ( 5 $ 7 8 5 ( 8 6 $ * ( w g h v f u l s w l r q o d w h u l q w k l v ' 6 auto self refresh (asr) r s w l r q d o h [ w h q g h g w h p s h u d w x u h u d q j h r i ? & z k l o h l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h 7 k h v w d q g d u g 6 ( / ) 5 ( ) 5 ( 6 + f x u u h q w w h v w v s h f l i l h v w h v w f r q g l w l r q v w r q r u p d o d p e l h q w w h p s h u d w x u h ? & r q o \ p h d q l q j l i 6 5 7 l v h q d e o h g w k h v w d q g d u g 6 ( / ) 5 ( ) 5 ( 6 + f x u u h q w v s h f l i l f d w l r q v g r q r w d s s o \ srt vs. asr 0 r g h u h j l v w h u 0 5 > @ l v x v h g w r ' , 6 $ % / ( ( 1 $ % / ( w k h 6 5 7 i x q f w l r q : k h q 6 5 7 l v ' l v d e o h g w k h 6 ( / ) 5 ( ) 5 ( 6 + p r g h u v u h i u h v k u d w h l v d v v x p h g w r e h d w w k h q r u p d o ? & o l p l w , q w k h ' , 6 $ % / ( ' p r g h 6 5 7 u h t x l u h v w k h x v h u w r h q v x u h w k h 6 ' 5 $ 0 q h y h u h [ f h h g v w k h t $ o l p l w r i ? & z k l o h l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h x q o h v v w k h x v h u h q d e o h v $ 6 5 : k h q 6 5 7 l v h q d e o h g w k h 6 ' 5 $ 0 6 ( / ) 5 ( ) 5 ( 6 + l v f k d q j h g l q w h u q d o o \ i u r p ; w r ; u h j d u g o h v v r i w k h d p e l h q w w h p s h u d w x u h 7 $ 7 k l v h q d e o h v w k h x v h u w r r s h u d w h w k h 6 ' 5 $ 0 e h \ r q g w k h v w d q g d u g ? & o l p l w x s w r w k h self refresh temperature (srt) , i w k h q r u p d o d p e l h q w w h p s h u d w x u h o l p l w r i ? & l v q r w h [ f h h g h g w k h q q h l - w k h u 6 5 7 q r u $ 6 5 l v u h t x l u h g d q g e r w k f d q e h ' , 6 $ % / ( ' w k u r x j k r x w r s h u d w l r q , i w k h h [ w h q g h g w h p s h u d w x u h r s w l r q l v x v h g w k h x v h u l v u h t x l u h g w r s u r y l g h d ; u h i u h v k u d w h g x u l q j p d q x d o u h i u h v k i r u ( [ w h q g h g w h p s g h y l f h v r u ; u h i u h v k u d w h i r u 0 l o w h p s g h y l f h v 6 5 7 d q g $ 6 5 v k r x o g e h h q d e o h g i r u d x w r p d w l f 5 ( ) 5 ( 6 + v h u y l f h v r q d o o g h y l f h v x v h g l q w h p s h u d - w x u h h q y l u r q p h q w v d ? & 6 5 7 i r u f h v w k h 6 ' 5 $ 0 w r v z l w f k w k h l q w h u q d o 6 ( / ) 5 ( ) 5 ( 6 + u d w h i u r p ; w r ; 6 ( / ) 5 ( ) 5 ( 6 + l v s h u i r u p h g d w ; u h j d u g o h v v r i t $ . $ 6 5 d x w r p d w l f d o o \ v z l w f k h v w k h 6 ' 5 $ 0 u v l q w h u q d o 6 ( / ) 5 ( ) 5 ( 6 + u d w h i u r p ; w r ; k r z h y h u z k l o h l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h $ 6 5 h q d e o h v w k h 5 ( ) 5 ( 6 + u d w h d x w r p d w l f d o o \ d g m x v w e h w z h h q ; d q g ; 5 ( ) 5 ( 6 + u d w h r y h u w k h v x s s r u w h g w h p s h u d w x u h u d q j h 2 q h r w k h u g l v d g y d q w d j h z l w k $ 6 5 l v w k h 6 ' 5 $ 0 f d q q r w d o z d \ v v z l w f k i u r p d ; w r d ; u h i u h v k u d w h d w d q h [ d f w d p e l h q w 7 h p s h u d w x u h r i ? & $ o w k r x j k w k h 6 ' 5 $ 0 z l o o v x s s r u w g d w d l q w h j u l w \ z k h q l w v z l w f k h v i u r p d ; w r ; u d w h l w p d \ v z l w f k d w d o r z h u w h p s h u d w x u h w k d q ? & 6 l q f h r q o \ r q h p r g h l v q h f h v v d u \ d w r q h l q v w d q w l q w l p h 6 5 7 d q g $ 6 5 f d q q r w e h v l p x o w d q h r x v o \ h q d e o h g logic devices incorporated www.logicdevices.com 95 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product dynamic odt 7 k h p r g h u h j l v w h u 0 5 f r q w u r o v d g g l w l r q d o i x q f w l r q v d q g i h d w x u h v q r w d y d l o d e o h y l d 0 5 0 5 r u 0 5 & x u u h q w o \ g h i l q h g d v w k h 0 8 / 7 , 3 8 5 3 2 6 ( 5 ( * , 6 - 7 ( 5 0 3 5 7 k l v i x q f w l r q l v f r q w u r o o h g y l d w k h e l w v v k r z q l q ) l j x u h 7 k h 0 5 l v s u r j u d p p h g y l d w k h / 2 $ ' 0 2 ' ( f r p p d q g d q g u h w d l q v w k h v w r u h g l q i r u - p d w l r q x q w l o l w l v s u r j u d p p h g d j d l q r u x q w l o w k h g h y l f h o r v h v s r z h u 5 h s u r j u d p p l q j w k h 0 5 u h j l v w h u z l o o q r w d o w h u w k h f r q w h q w v r i w k h p h p r u \ d u u d \ s u r y l g h g w k h s u r j u d p p l q j r i w k h 0 5 k d v e h h q s h u i r u p h g f r u u h f w o \ 7 k h 0 5 u h j l v w h u p x v w e h o r d g h g z k h q d o o e d q n v d u h l g o h d q g q r g d w d e x u v w v d u h l q s u r j u h v v d q g w k h p h p r u \ f r q w u r o o h u p x v w z d l w w k h v s h f l i l h g w l p h t mrd and t 0 2 ' e h i r u h l q l w l d w l q j d v x e v h t x h q w r s h u d w l r q mode register (mr3) 7 k h g \ q d p l f 2 ' 7 5 tt b : 5 i h d w x u h l v g h i l q h g e \ 0 5 > @ ' \ q d p l f 2 ' 7 l v h q d e o h g z k h q d y d o x h l v v h o h f w h g 7 k l v q h z ' ' 5 i h d w x u h h q d e o h v w k h 2 ' 7 w h u p l q d w l r q y d o x h w r f k d q j h z l w k r x w l v v x l q j d q 0 5 6 f r p p d q g h v v h q w l d o o \ f k d q j l q j w k h 2 ' 7 w h u p l q d w l r q v r q w k h i o \ w : l w k g \ q d p l f 2 ' 7 5 tt b : 5 z k h q e h j l q q l q j d : 5 , 7 ( e x u v w d q g v x e v h t x h q w o \ v z l w f k h v e d f n w r 2 ' 7 5 tt b : 5 l v h q d e o h g 2 ' 7 / & 1 : 2 ' 7 / & 1 : 2 ' 7 / & 1 : 2 ' 7 + 2 ' 7 + d q g t $ ' & ' \ q d p l f 2 ' 7 l v r q o \ d s s o l f d e o h g x u l q j : 5 , 7 ( f \ f o h v , i 2 ' 7 5 tt b 1 2 0 l v g l v d e o h g g \ q d p l f 2 ' 7 5 tt b : 5 l v v w l o o s h u p l w w h g 5 tt _nom and r tt b : 5 f d q e h x v h g l q g h s h q g h q w r i r q h d q r w k h u ' \ q d p l f 2 ' 7 l v q r w d y d l o d e o h g x u l q j : 5 , 7 ( / ( 9 ( / , 1 * p r g h u h j d u g o h v v r i w k h v w d w h r i 2 ' 7 5 tt b 1 2 0 ) r u g h w d l o v r q 2 ' 7 r s h u d w l r q u h i h u w r w k h v 2 q ' l h 7 h u p l q d w l r q 2 ' 7 w v h f w l r q f igure 50 - m ode r egister 3 (mr3) d efinition a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mode register 3 (mr3) add ress bus 976543 8210 a10 a12 a11 1a b0 ab 10 11 121314 15 a13 10 1 0 1 0 1 0 1 0 1 0 1 0 1 mpr 1 ba2 16 0 1 0 1 0 1 0 1 0 1 m2 0 1 mpr enable normal dram operations 2 dataflow from mpr mpr_rf m14 0 1 0 1 m15 0 0 1 1 mode register mo de register set (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) mpr read func tion predefined pattern 3 reserved reserved reserved m0 0 1 0 1 m1 0 0 1 1 1 2 7 ( 6 1. 0 5 > d q g @ d u h u h v h u y h g i r u i x w x u h x v h d q g p x v w d o o e h s u r j u d p p h g w r v w 2. : k h q 0 3 5 f r q w u r o l v v h w i r u q r u p d o ' 5 $ 0 r s h u d w l r q 0 5 > @ z l o o e h l j q r u h g 3. , q w h q g h g w r e h x v h g i r u 5 ( $ ' v \ q f k u r q l ] d w l r q logic devices incorporated www.logicdevices.com 96 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product multipurpose register (mpr) 7 k h 0 8 / 7 , 3 8 5 3 2 6 ( 5 ( * , 6 7 ( 5 i x q f w l r q l v x v h g w r r x w s x w d s u h g h i l q h g v \ v w h p w l p l q j f d o l e u d w l r q e l w v h t x h q f h % l w l v w k h p d v w h u e l w w k d w h q d e o h v r u g l v d e o h v d f f h v v w r w k h 0 3 5 u h j l v w h u d q g e l w v d q g g h w h u p l q h z k l f k p r g h w k h 0 3 5 l v s o d f h g l q 7 k h e d v l f f r q f h s w r i w k h p x o w l s x u s r v h u h j l v w h u l v v k r z q l q ) l j x u h , i 0 5 > @ l v d v w w k h q w k h 0 3 5 d f f h v v l v g l v d e o h g d q g w k h 6 ' 5 $ 0 r s h u d w h v l q q r u p d o p r g h + r z h y h u l i 0 5 > @ l v d v w w k h q 6 ' 5 $ 0 q r o r q j h u r x w s x w v q r u p d o u h d g g d w d e x w r x w s x w v 0 3 5 g d w d d v g h i l q h g e \ 0 5 > @ , i 0 5 > @ l v h t x d o w r v w w k h q d s u h g h i l q h g u h d g s d w w h u q i r u v \ v w h p f d o l e u d w l r q l v v h o h f w h g 7 r h q d e o h w k h 0 3 5 w k h 0 5 6 f r p p d q g l v l v v x h g w r 0 5 d q g 0 5 > @ v h h 7 d e o h 3 u l r u w r l v v x l q j w k h 0 5 6 f r p p d q g d o o e d q n v p x v w e h l q w k h l g o h v w d w h d o o e d q n v d u h s u h f k d u j h g d q g t 5 3 l v p h w : k h q w k h 0 3 5 l v h q d e o h g d q \ v x e v h t x h q w 5 ( $ ' r u 5 ' $ 3 f r p p d q g v d u h u h g l u h f w h g w r w k h p x o w l s x u s r v h u h j l v w h u 7 k h u h v x o w l q j r s h u d w l r q z k h q h l w k h u d 5 ( $ ' r u d 5 ' $ 3 f r p p d q g l v l v v x h g l v g h i l q h g e \ 0 5 > @ z k h q 0 3 5 l v h q d e o h g v h h 7 d e o h : k h q w k h 0 3 5 l v h q d e o h g r q o \ 5 ( $ ' r u 5 ' $ 3 f r p p d q g v d u h d o o r z h g x q w l o d v x e v h t x h q w 0 5 6 f r p p d q g l v l v v x h g z l w k w k h 0 3 5 g l v d e o h g 0 5 > @ 3 2 : ( 5 ' 2 : 1 6 ( / ) 5 ( ) 5 ( 6 + d q g d q \ r w k h u 1 2 1 5 ( $ ' r u 5 ' $ 3 f r p p d q g l v q r w d o o r z h g 7 k h 5 ( 6 ( 7 i x q f w l r q l v v x s s r u w h g g x u l q j 0 3 5 h q d e o h p r g h f igure 51 - m ultipurpose r egister (mpr) b lock d iagram memory core mr3[2] = 0 (mpr off) dq, dm, dq s, dqs# multipurpose register pre defined data for reads mr3[2] = 1 (mpr on) 1 2 7 ( 6 1. $ s u h g h i l q h g g d w d s d w w h u q f d q e h u h d g r x w r i w k h 0 3 5 z l w k d q h [ w h u q d o 5 ( $ ' f r p p d q g 2. 0 5 > @ g h i l q h v z k h w k h u w k h g d w d i o r z f r p h v i u r p w k h p h p r u \ f r u h r u w k h 0 3 5 : k h q w k h g d w d i o r z l v g h i l q h g w k h 0 3 5 f r q w h q w v f d q e h u h d g r x w f r q w l q x r x v o \ z l w k d u h j x o d u 5 ( $ ' r u 5 ' $ 3 f r p p d q g logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product mpr mpr read function function 0 1 1 r u p d o 2 s h u d w l r q q r 0 3 5 w u d q v d f w l r q $ o o v x e v h t x h q w 5 ( $ ' v f r p h i u r p w k h 6 ' 5 $ 0 p h p r u \ d u u d \ $ o o v x e v h t x h q w : 5 , 7 ( v j r w r w k h 6 ' 5 $ 0 p h p r u \ d u u d \ ( q d e o h 0 3 5 p r g h v x e v h t x h q w 5 ( $ ' 5 ' $ 3 f r p p d q g v g h i l q h g e \ e l w v and 2. t able 61: burst order v ' r q u w & d u h w $ > @ 6 h h 7 d e o h mr3[2] mr3[1:0] mpr functional description 7 k h 0 3 5 - ( ' ( & g h i l q l w l r q d o o r z v i r u h l w k h u d s u l p h ' 4 i r u o r z h u e \ w h d q g ' 4 i r u w k h x s s h u e \ w h r i h d f k r i w k h z r u g v f r q w d l q h g l q w k h / ' , l 0 2 ' w r r x w s x w w k h 0 3 5 g d w d z l w k w k h u h p d l q l q j ' 4 v g u l y h q / 2 : r u i r u d o o ' 4 v w r r x w s x w w k h 0 3 5 g d w d 7 k h 0 3 5 u h d g r x w v x s s r u w v i l [ h g 5 ( $ ' e x u v w d q g 5 ( $ ' e x u v w f k r s 0 5 6 d q g 2 7 ) y l d $ % & z l w k u h j x o d u 5 ( $ ' o d w h q f l h v d q g $ & w l p l q j v d s s o l f d e o h 7 k l v s u r y l g l q j w k h ' / / l v o r f n h g d v u h t x l u h g 0 3 5 d g g u h v v l q j i r u d y d o l g 0 3 5 5 ( $ ' l v d v i r o o r z v x $ > @ p x v w e h v h w w r v w d v w k h e x u v w r u g h u l v i l [ h g s h u q l e e o h x $ v h o h f w v w k h e x u v w r u g h u x % / $ l v v h w w r v w d q g w k h e x u v w r u g h u l v i l [ h g w r x ) r u e x u v w f k r s f d v h v w k h e x u v w r u g h u l v v z l w f k h g r q w k h q l e e o h e d v h d q g x $ e x u v w r u g h u x $ e x u v w r u g h u x % x u v w r u g h u e l w w k h i l u v w e l w l v d v v l j q h g w r / 6 % d q g e x u v w r u g h u e l w w k h o d v w e l w l v d v v l j q h g w r 0 6 % x $ > @ d u h d v ' r q u w & d u h w x $ l v d v ' r q u w & d u h w x $ l v d v ' r q u w & d u h w x $ 6 h o h f w v e x u v w f k r s p r g h r q w k h i o \ l i h q d e o h g z l w k l q 0 5 x $ l v d v ' r q u w & d u h w x % $ > @ d u h d v ' r q u w & d u h w logic devices incorporated www.logicdevices.com 98 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product mpr register address definitions and bursting order 7 k h 0 3 5 f x u u h q w o \ v x s s r u w v d v l q j o h g d w d i r u p d w 7 k l v g d w d i r u p d w l v d s u h g h i l q h g 5 ( $ ' s d w w h u q i r u v \ v w h p f d o l e u d w l r q 7 k h s u h g h i l q h g s d w w h u q l v d o z d \ v d u h s h d w l q j e l w s d w w h u q ( [ d p s o h v r i w k h g l i i h u h q w w \ s h r i s u h g h i l q h g 5 ( $ ' s d w w h u q e x u v w v d u h v k r z q l q ) l j x u h v d q g mr3[2] mr3[1:0] function length a[2:0] burst order and data pattern 1 1 1 1 % x u v w 2 u g h u 3 u h g h i l q h g s d w w h u q burst order: 0,1,2,3 3 u h g h i l q h g s d w w h u q % x u v w 2 u g h u 3 u h g h i l q h g s d w w h u q n/a n/a n/a n/a n/a n/a n/a n/a n/a t able 62: burst order 5 ( $ ' s u h g h i l q h g s d w w h u q i r u v \ v w h p f d o l e u d w l r q 5 ) 8 5 ) 8 5 ) 8 bl8 % & % & n/a n/a n/a n/a n/a n/a n/a n/a n/a 000 000 100 n/a n/a n/a n/a n/a n/a n/a n/a n/a 00 01 10 11 burst read logic devices incorporated www.logicdevices.com 99 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. read with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. t0 ta0 tb0 tb 1 tc0 tc1 tc2 tc3 tc4 tc5 tc 6 tc7 tc8 tc9 tc1 0 ck ck # mrs prea read 1 nop nop nop nop nop nop nop nop mrs nop nop valid command t mprr don t care indicates a break in time scale dqs, dqs# bank add ress 3 vali d 3 0 a[1:0] vali d 0 2 1 a2 0 2 0 00 a[9:3] vali d 00 0 1 a10/ap vali d 0 0i lav 11a d 0 0 a12/bc# vali d 1 0 0i lav ]31:51[a d 0 dq t mod t rp t mod rl figure 52 - mpr system read calibration with bl8: fixed burst order single readout logic devices incorporated www.logicdevices.com 100 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. read with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc 6 tc7 tc8 tc9 tc1 0 td ck ck# t mprr don t care indicates a break in time scale rl 3 vali d 3 bank add ress vali d a[1:0] vali d 0 2 0 2 0 a2 1 2 0 2 1 0 0 a[15:13] vali d vali d 0 a[9:3] vali d vali d 00 00 a11 vali d vali d 0 0 a12/bc# vali d 1 0 0 a10/ap vali d vali d 0 0 1 rl prea read 1 nop nop nop no nop nop nop mrs vali d command read 1 mrs dq vali d dqs, dqs# t rp t mod t ccd t mod nop nop figure 53 - mpr system read calibration with bl8: fixed burst order, back-to-back readout logic devices incorporated www.logicdevices.com 101 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. read with bc4 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a2 = 0 selects lower 4 nibble bits 0 . . . 3. 4. a2 = 1 selects upper 4 nibble bits 4 . . . 7. t0 ta tb ck ck# dq dqs, dqs# t mod t mprr don t care tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 tc9 tc10 td nop nop nop nop valid command mrs prea read 1 read 1 nop nop indicates a break in time scale bank add ress 3 vali d 3 vali d 0 a[1:0] vali d 0 2 0 2 1 a2 1 4 0 3 0 00 ilav ]3:9[a d vali d 00 0 1i lav pa/01a d vali d 0 0i lav 11a d vali d 0 0 a12/bc# vali d 1 vali d 1 0 0 a[15:13] vali d vali d 0 rl rl t rf t mod t ccd nop nop mrs nop figure 54 - mpr system read calibration with bc4: lower nibble, then upper nibble logic devices incorporated www.logicdevices.com 102 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. read with bc4 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a2 = 1 selects upper 4 nibble bits 4 . . . 7. 4. a2 = 0 selects lower 4 nibble bits 0 . . . 3. t0 ta tb 0 1i lav pa/01a dvalid 0 ck ck# mrs prea read 1 read 1 nop nop nop s nop nop valid command 0 0 4 1 3 1 a2 t mod t mprr 3valid 3 bank add ress vali d 0 2 0 2 0 a[1:0] vali d 0 0i lav ]31:51[a dvalid 0 0i lav 11a d vali d 00 00 ilav ]3:9[a dvalid don t care tc0tc1tc2tc3tc4tc5tc6tc7tc8tc9tc10td indicates a break in time scale rl dq dqs, dqs# 0 a12/bc# vali d 1 vali d 1 0 rl t rf t mod t ccd mr nop nop nop nop figure 55 - mpr system read calibration with bc4: upper nibble, then lower nibble logic devices incorporated www.logicdevices.com 103 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product mpr read predefined pattern 7 k h s u h g h w h u p l q h g 5 ( $ ' f d o l e u d w l r q s d w w h u q l v d i l [ h g s d w w h u q r i 7 k h i r o o r z l q j l v d q h [ d p s o h r i x v l q j w k h 5 ( $ ' r x w s u h g h w h u p l q h g 5 ( $ ' f d o l e u d w l r q s d w w h u q 7 k h h [ d p s o h l v w r s h u i r u p p x o w l s o h 5 ( $ ' 6 i u r p w k h 0 8 / 7 , 3 8 5 3 2 6 ( 5 ( * , 6 7 ( 5 0 3 5 l q r u g h u w r g r v \ v w h p o h y h o 5 ( $ ' w l p l q j f d o l e u d - w l r q e d v h g r q w k h s u h g h w h u p l q h g d q g v w d q g d u g l ] h g s d w w h u q 7 k h i r o o r z l q j s u r w r f r o r x w o l q h v w k h v w h s v x v h g w r s h u i r u p w k h 5 ( $ ' f d o l e u d w l r q x 3 u h f k d u j h d o o e d q n v x $ i w h u t 5 3 l v v d w l v i l h g v h w 0 5 6 0 5 > @ d q g 0 5 > @ 7 k l v u h g l u h f w v d o o v x e v h t x h q w 5 ( $ ' v d q g / r d g v w k h s u h g h i l q h g s d w w h u q l q w r w k h 0 3 5 $ v v r r q d v t mrd and t 0 2 ' d u h v d w l v i l h g w k h 0 3 5 l v d y d l o d e o h x ' d w d : 5 , 7 ( r s h u d w l r q v d u h q r w d o o r z h g x q w l o w k h 0 3 5 u h w x u q v w r w k h q r u p d o 6 ' 5 $ 0 v w d w h x , v v x h d 5 ( $ ' z l w k e x u v w r u g h u l q i r u p d w l r q d o o r w k h u d g g u h v v s l q v d u h v ' r q u w & d u h w x $ > @ g d w d e x u v w r u g h u l v i l [ h g v w d u w l q j d w q l e e o h x $ i r u % / e x u v w r u g h u l v i l [ h g d v x $ x v h % / x $ i w h u 5 / $ / & / w k h 6 ' 5 $ 0 e x u v w v r x w w k h s u h g h i l q h g 5 ( $ ' f d o l e u d w l r q s d w w h u q x 7 k h p h p r u \ f r q w u r o o h u u h s h d w v w k h f d o l e u d w l r q 5 ( $ ' v x q w l o 5 ( $ ' g d w d f d s w x u h d w w k h p h p r u \ f r q w u r o o h u l v r s w l p l ] h g x $ i w h u w k h o d v w 0 3 5 5 ( $ ' e x u v w d q g d i w h u t 0 3 5 5 k d v e h h q v d w l v i l h g l v v x h 0 5 6 0 5 > @ d q g 0 5 > @ v ' r q u w & d u h w w r w k h q r u p d o 6 ' 5 $ 0 v w d w h $ o o v x e v h t x h q w 5 ( $ ' d q g : 5 , 7 ( d f f h v v h v z l o o e h u h j x o d u 5 ( $ ' 6 d q g : 5 , 7 ( 6 i u r p w r w k h 6 ' 5 $ 0 d u u d \ x : k h q t mrd and t 0 2 ' d u h v d w l v i l h g i u r p w k h o d v w 0 5 6 w k h u h j x o d u 6 ' 5 $ 0 f r p p d q g v v x f k d v $ & 7 , 9 $ 7 ( d 0 h p r u \ e d q n i r u u h j x o d u 5 ( $ ' r u : 5 , 7 ( d f f h v v d u h s h u p l w w h g mode register set (mrs) 7 k h p r g h u h j l v w h u v d u h o r d g h g y l d l q s x w v % $ > @ $ > @ % $ > @ g h w h u p l q h v z k l f k p r g h u h j l v w h u l v s u r j u d p p h g x % $ % $ % $ i r u 0 5 x % $ % $ % $ i r u 0 5 x % $ % $ % $ i r u 0 5 x % $ % $ % $ i r u 0 5 7 k h 0 5 6 f r p p d q g f d q r q o \ e h l v v x h g r u u h l v v x h g z k h q d o o e d q n v d u h l g o h d q g l q w k h s u h f k d u j h g v w d w h t 5 3 l v v d w l v i l h g d q g q r g d w d e x u v w v d u h l q s u r j u h v v 7 k h f r q w u r o o h u p x v w z d l w w k h v s h f l i l h g w l p h t 0 5 ' e h i r u h l q l w l d w l q j d v x e v h t x h q w r s h u d w l r q v x f k d v d q $ & 7 , 9 $ 7 ( f r p p d q g 7 k h u h l v d o v r d u h v w u l f w l r q d i w h u l v v x l q j d q 0 5 6 f r p p d q g z l w k u h j d u g w r z k h q w k h x s g d w h g i x q f w l r q v e h f r p h d y d l o d e o h 7 k l v s d u d p h w h u l v v s h f l i l h g e \ t mod. both t mrd and t 0 2 ' s d u d p h w h u v d u h v k r z q l q ) l j x u h d q g 9 l r o d w l q j h l w k h u r i w k h v h u h t x l u h p h q w v z l o o u h v x o w l q x q v s h f l i l h g r s h u d w l r q zq calibration 7 k h = 4 & $ / , % 5 $ 7 , 2 1 f r p p d q g l v x v h g w r f d o l e u d w h w k h 6 ' 5 $ 0 r x w s x w g u l y h u v 5 2 1 d q g 2 ' 7 y d o x h v 5 tt r y h u s u r f h v v y r o w d j h d q g w h p s h u d w x u h s u r - y l g h g d g h g l f d w h g : ? h [ w h u q d o u h v l v w r u l v f r q q h f w h g i u r p w k h 6 ' 5 $ 0 u v = 4 e d o o w r 9 v v 4 ' ' 5 6 ' 5 $ 0 v q h h g d o r q j h u w l p h w r f d o l e u d w h 5 on d q g 2 ' 7 d w s r z h u x s , 1 , 7 , $ / , = $ 7 , 2 1 d q g 6 ( / ) 5 ( ) 5 ( 6 + h [ l w d q g d u h o d w l y h o \ v k r u w h u w l p h w r s h u i r u p s h u l r g l f f d o l e u d w l r q v ' ' 5 6 ' 5 $ 0 g h i l q h v w z r = 4 & $ / , % 5 $ 7 , 2 1 f r p p d q g v = 4 & $ / , % 5 $ 7 , 2 1 / 2 1 * = 4 & / d q g = 4 & $ / , % 5 $ 7 , 2 1 6 + 2 5 7 = 4 & 6 $ q h [ d p s o h r i = 4 & $ / , % 5 $ 7 , 2 1 w l p l q j l v v k r z q l q ) l j x u h $ o o e d q n v p x v w e h 3 5 ( & + $ 5 * ( ' d q g t 5 3 p x v w e h p h w e h i r u h = 4 & / r u = 4 & 6 f r p p d q g v f d q e h l v v x h g w r w k h 6 ' 5 $ 0 1 r r w k h u d f w l y l w l h v r w k h u w k d q d q r w k h u = 4 & / r u = 4 & 6 f r p p d q g p d \ e h l v v x h g w r w k h 6 ' 5 $ 0 f d q e h s h u i r u p h g r q w k h 6 ' 5 $ 0 d u u d \ e \ w k h f r q w u r o o h u i r u w k h g x u d w l r q r i t = 4 , 1 , 7 r u t = 4 2 3 ( 5 7 k h t x l h w w l p h r q w k h 6 ' 5 $ 0 d u u d \ k h o s v d f f x u d w h o \ f d o l e u d w h 5 on d q g 2 ' 7 $ i w h u 6 ' 5 $ 0 f d o l e u d w l r q l v d f k l h y h g w k h 6 ' 5 $ 0 v k r x o g g l v d e o h w k h = 4 e d o o u v f x u u h q w f r q v x p s w l r q s d w k w r u h g x f h r y h u d o o s r z h u x v d j h = 4 & $ / , % 5 $ 7 , 2 1 f r p p d q g v f d q e h l v v x h g l q s d u d o o h o w r ' / / 5 ( 6 ( 7 d q g o r f n l q j w l p h 8 s r q 6 ( / ) 5 ( ) 5 ( 6 + h [ l w d q h [ s o l f l w = 4 & / l v u h t x l u h g l i = 4 & $ / , - % 5 $ 7 , 2 1 l v g h v l u h g , q g x d o u d q n v \ v w h p g h v l j q v w k d w v k d u h w k h = 4 u h v l v w r u e h w z h h q g h y l f h v w k h f r q w u r o o h u p x v w q r w d o o r z r y h u o d s r i t = 4 , 1 7 t = 4 2 3 ( 5 r u t = 4 & 6 e h w z h h q u d q n v logic devices incorporated www.logicdevices.com 104 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 56 - zq c alibration t iming (zqcl and zqcs) nop zqcl nop nop valid vali d zqcs nop nop nop valid command indicates a break in time scale t0 t1 ta0 ta1 ta2 ta3 tb0 tb1 tc0 tc1 tc2 address vali d vali d vali d a10 vali d vali d vali d ck ck# don t care dq high-z high-z 3 a 3 ctivities activ- ities vali d vali d odt 2 2 vali d 1 ck e 1 vali d vali d vali d t zqcs t zq init or t zq oper 1 2 7 ( 6 1. & . ( p x v w e h f r q w l q x r x v o \ u h j l v w h u h g + , * + g x u l q j w k h f d o l e u d w l r q s u r f h g x u h 2. 2 ' 7 p x v w e h g l v d e o h g y l d w k h 2 ' 7 v l j q d o r u w k h 0 5 6 g x u l q j w k h f d o l e u d w l r q s u r f h g x u h 3. $ o o g h y l f h v f r q q h f w h g w r w k h ' 4 e x v v k r x o g e h + l j k = g x u l q j f d o l e u d w l r q activate % h i r u h d q \ 5 ( $ ' r u : 5 , 7 ( f r p p d q g v f d q e h l v v x h g w r d e d q n z l w k l q w k h 6 ' 5 $ 0 d 5 2 : l q w k d w e d q n p x v w e h r s h q h g $ & 7 , 9 $ 7 ( ' 7 k l v l v d f f r p s o l v k h g y l d w k h $ & 7 , 9 $ 7 ( f r p p d q g z k l f k v h o h f w v e r w k w k h % $ 1 . d q g w k h 5 2 : w r e h $ & 7 , 9 $ 7 ( ' $ i w h u d 5 2 : l v r s h q h g z l w k d q $ & 7 , 9 $ 7 ( f r p p d q g d 5 ( $ ' r u : 5 , 7 ( f r p p d q g p d \ e h l v v x h g w r w k d w 5 2 : v x e m h f w w r w k h t 5 & ' v s h f l i l f d w l r q + r z h y h u l i w k h d g g l w l y h o d w h q f \ l v s u r j u d p p h g f r u u h f w o \ d 5 ( $ ' r u : 5 , 7 ( f r p p d q g p d \ e h l v v x h g s u l r u w r t 5 & ' 0 , 1 , q w k l v r s h u d w l r q w k h 6 ' 5 $ 0 h q d e o h v d 5 ( $ ' r u : 5 , 7 ( f r p p d q g w r e h l v v x h g d i w h u w k h $ & 7 , 9 $ 7 ( f r p p d q g i r u w k d w e d q n e x w s u l r u w r t 5 & ' 0 , 1 v h h v 3 2 6 7 ( ' & $ 6 $ ' ' , 7 , 9 ( / $ 7 ( 1 & < $ / t 5 & ' 0 , 1 v k r x o g e h g l y l g h g e \ w k h f o r f n s h u l r g d q g u r x q g h g x s w r w k h q h [ w z k r o h q x p e h u w r g h w h u p l q h w k h h d u o l h v w f o r f n h g j h d i w h u w k h $ & 7 , 9 $ 7 ( f r p p d q g r q z k l f k w k h 5 ( $ ' r u : 5 , 7 ( f r p p d q g f d q e h h q w h u h g 7 k h v d p h s u r f h g x u h l v x v h g w r f r q y h u w r w k h u v s h f l i l f d w l r q o l p l w v i u r p w l p h x q l w v w r f o r f n f \ f o h v : k h q d w o h d v w r q h e d q n l v r s h q d q \ 5 ( $ ' w r 5 ( $ ' f r p p d q g g h o d \ r u : 5 , 7 ( w r : 5 , 7 ( f r p p d q g g h o d \ l v u h v w u l f w h g w r t & & ' 0 , 1 $ v x e v h t x h q w $ & 7 , 9 $ 7 ( f r p p d q g w r d g l i i h u h q w 5 2 : l q w k h v d p h % $ 1 . f d q r q o \ e h l v v x h g d i w h u w k h s u h y l r x v $ & 7 , 9 ( 5 2 : k d v e h h q f o r v h g 3 5 ( - & + $ 5 * ( ' 7 k h p l q l p x p w l p h l q w h u y d o e h w z h h q v x f f h v v l y h $ & 7 , 9 $ 7 ( f r p p d q g v w r w k h v d p h % $ 1 . l v g h i l q h g e \ t 5 & $ v x e v h t x h q w $ & 7 , 9 $ 7 ( f r p p d q g w r d q r w k h u % $ 1 . f d q e h l v v x h g z k l o h w k h i l u v w % $ 1 . l v e h l q j d f f h v v h g z k l f k u h v x o w v l q d u h g x f w l r q r i w r w d o 5 2 : $ & & ( 6 6 r y h u k h d g 7 k h p l q l p x p w l p h l q w h u y d o e h w z h h q v x f f h v v l y h $ & 7 , 9 $ 7 ( f r p p d q g v p d \ e h l v v x h g l q d j l y h q t ) $ : 0 , 1 s h u l r g d q g w k h t 5 5 ' 0 , 1 u h v w u l f w l r q still applies. the t ) $ : 0 , 1 s d u d p h w h u d s s o l h v u h j d u g o h v v r i w k h q x p e h u r i % $ 1 . 6 d o u h d g \ r s h q h g r u f o r v h g logic devices incorporated www.logicdevices.com 105 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 57 - e xample : m eeting t rrd (min) and t rcd (min) command don t care t1 t0 t2 t3 t4 t5 t8 t9 t rrd row row co l bank x bank y bank y nop act nop nop act nop nop rd/wr t rcd ba[2:0] ck # add ress ck t10 t11 nop nop indicates a break in time scale f igure 58 - e xample : t faw command don t care t1 t0 t4 t5 t8 t9 t10 t11 t rrd row row bank a bank b row bank c row bank d bank y row bank y nop act nop ac a tctnop nop t faw ba[2:0] ck # add ress ck t19 t20 nop ac a tc t bank e indicates a break in time scale logic devices incorporated www.logicdevices.com 106 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 59 - read l atency notes: 1. do n = data-out from column n. 2. subsequent elements of data-out appear in the programmed order following do n. . ck ck # command read nop nop nop nop nop nop nop add ress bank a, col n cl = 8, al = 0 dq dqs, dqs# do n t0 t7 t8 t9 t10 t11 don t care transitioning data t12 t12 indicates a break in time scale read 5 ( $ ' e x u v w v d u h l q l w l d w h g z l w k d 5 ( $ ' f r p p d q g 7 k h v w d u w l q j & 2 / 8 0 1 d q g % $ 1 . d g g u h v v h v d u h s u r y l g h g z l w k w k h 5 ( $ ' f r p p d q g d q g $ 8 7 2 3 5 ( - & + $ 5 * ( l v h l w k h u h q d e o h g r u g l v d e o h g i r u w k d w e x u v w d f f h v v , i $ 8 7 2 3 5 ( & + $ 5 * ( l v h q d e o h g w k h 5 2 : e h l q j d f f h v v h g l v d x w r p d w l f d o o \ 3 5 ( & + $ 5 * ( ' d w w k h f r p s o h w l r q r i w k h e x u v w v h t x h q f h , i $ 8 7 2 3 5 ( & + $ 5 * ( l v g l v d e o h g w k h 5 2 : z l o o e h o h i w r s h q d i w h u w k h f r p s o h w l r q r i w k h e x u v w ' x u l q j 5 ( $ ' e x u v w v w k h y d o l g g d w d r x w h o h p h q w i u r p w k h v w d u w l q j f r o x p q d g g u h v v l v d y d l o d e o h d w 5 ( $ ' / $ 7 ( 1 & < 5 / f o r f n v o d w h u 5 / l v g h i l q h g d v w k h v x p r i 3 2 6 7 ( ' & $ 6 $ ' ' , 7 , 9 ( / $ 7 ( 1 & < $ / d q g & $ 6 / $ 7 ( 1 & < & / 5 / $ / & / 7 k h y d o x h r i $ / d q g & / l v s u r j u d p p d e o h l q w k h p r g h u h j l v w h u y l d w k h 0 5 6 f r p p d q g ( d f k v x e v h t x h q w g d w d r x w h o h p h q w z l o o e h y d o l g q r p l q d o o \ d w w k h q h [ w s r v l w l y h r u q h j d w l y h f o r f n h g j h w k d w l v d w w k h q h [ w f u r v v l q j r i & . d q g & . ? ) l j x u h v k r z v d q h [ d p s o h r i 5 / e d v h g r q d & / v h w w l q j r i d v z h o o d v $ / $ 5 ( $ ' e x u v w p d \ e h i r o o r z h g e \ d 3 5 ( & + $ 5 * ( f r p p d q g w r w k h v d p h e d q n s u r y l g h g $ 8 7 2 3 5 ( & + $ 5 * ( l v q r w $ & 7 , 9 $ 7 ( ' 7 k h p l q l p x p 5 ( $ ' w r 3 5 ( & + $ 5 * ( f r p p d q g v s d f l q j w r w k h v d p h e d q n l v i r x u f o r f n v d q g p x v w d o v r v d w l v i \ d p l q l p x p d q d o r j w l p h i u r p w k h 5 ( $ ' f r p p d q g 7 k l v w l p h l v f d o o h g t 5 7 3 5 ( $ ' w r 3 5 ( & + $ 5 * ( t 5 7 3 v w d u w v $ / f \ f o h v o d w h u w k d q w k h 5 ( $ ' f r p p d q g ( [ d p s o h v i r u % / d u h v k r z q l q ) l j x u h d q g % & l q ) l j x u h ) r o o r z l q j w k h 3 5 ( & + $ 5 * ( f r p p d q g d v x e v h - t x h q w f r p p d q g w r w k h v d p h e d q n f d q q r w e h l v v x h g x q w l o t 5 3 l v p h w 7 k h 3 5 ( & + $ 5 * ( f r p p d q g i r o o r z h g e \ d q r w k h u 3 5 ( & + $ 5 * ( f r p p d q g w r w k h v d p h e d q n l v d o o r z h g + r z h y h u w k h s u h f k d u j h s h u l r g z l o o e h g h w h u - p l q h g e \ w k h o d v w 3 5 ( & + $ 5 * ( f r p p d q g l v v x h g w r w k h e d q n , i $ l v + , * + z k h q d 5 ( $ ' f r p p d q g l v l v v x h g w k h 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( i x q f w l r q l v h q j d j h g 7 k h 6 ' 5 $ 0 v w d u w v d q $ 8 7 2 3 5 ( - & + $ 5 * ( r s h u d w l r q r q w k h u l v l q j h g j h z k l f k l v $ / t 5 7 3 f \ f o h v d i w h u w k h 5 ( $ ' f r p p d q g ' ' 5 6 ' 5 $ 0 v v x s s r u w d t 5 $ 6 o r f n r x w i h d w x u h v h h ) l j x u h , i t 5 $ 6 0 , 1 l v q r w v d w l v i l h g d w w k h h g j h w k h v w d u w l q j s r l q w r i w k h $ 8 7 2 3 5 ( & + $ 5 * ( r s h u d w l r q z l o o e h g h o d \ h g x q w l o t 5 $ 6 0 , 1 l v v d w - l v i l h g , q f d v h w k h l q w h u q d o 3 5 ( & + $ 5 * ( r s h u d w l r q l v s x v k h g r x w e \ t rtp, t 5 3 v w d u w v d w w k h s r l q w d w z k l f k w k h l q w h u q d o 3 5 ( & + $ 5 * ( k d s s h q v 7 k h w l p h i u r p 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( w r w k h q h [ w $ & 7 , 9 $ 7 ( f r p - p d q g w k h v d p h e d q n l v $ / t 5 7 3 t 5 3 z k h u h v w p h d q v u r x q g h g x s w r w k h q h [ w l q w h j h u , q d q \ h y h q w l q w h u q d o 5 ( & + $ 5 * ( g r h v q r w v w d u w h d u o l h u w k d q i r x u f o r f n v d i w h u w k h o d v w q e l w s u h i h w f k / > 8 @ ' 4 6 [ / > 8 @ ' 4 6 [ ? l v g u l y h q e \ w k h 6 ' 5 $ 0 d o r q j z l w k w k h r x w s x w g d w d 7 k h l q l w l d o / 2 : v w d w h r q / > 8 @ ' 4 6 [ d q g + , * + v w d w h r q / > 8 @ ' 4 6 [ ? l v n q r z q d v w k h 5 ( $ ' s u h d p e o h t 5 3 5 ( 7 k h / 2 : v w d w h r q ' 4 6 [ d q g w k h + , * + v w d w h r q / > 8 @ ' 4 6 [ ? f r l q f l g h q w z l w k w k h o d v w g d w d r x w h o h p h q w l v n q r z q d v w k h 5 ( $ ' s r v w d p e o h t 5 3 6 7 8 s r q f r p s o h w l r q r i d e x u v w d v v x p l q j q r r w k h u f r p p d q g v k d y h e h h q l q l w l d w h g w k h ' 4 z l o o j r + , * + = $ g h w d l o h g h [ s o d q d w l r q r i t ' 4 6 4 y d o l g g d w d r x w v n h z t 4 + g d w d r x w z l q g r z k r o g d q g w k h y d o l g g d w d z l q g r z d u h g h s l f w h g l q ) l j x u h $ g h w d l o h g h [ s o d q d - w l r q r i t ' 4 6 & . ' 4 6 w u d q v l w l r q v n h z w r & . l v d o v r g h s l f w h g l q ) l j x u h ' d w d i u r p d q \ 5 ( $ ' e x u v w p d \ e h f r q f d w h q d w h g z l w k g d w d i u r p d v x e v h - t x h q w 5 ( $ ' f r p p d q g w r s u r y l g h d f r q w l q x r x v i o r z r i g d w d 7 k h i l u v w g d w d h o h p h q w i u r p w k h q h z e x u v w i r o o r z v w k h o d v w h o h p h q w r i d f r p s o h w h g e x u v w 7 k h q h z 5 ( $ ' f r p p d q g v k r x o g e h l v v x h g t & & ' f \ f o h v d i w h u w k h i l u v w 5 ( $ ' f r p p d q g 7 k l v l v v k r z q i r u % / l q ) l j x u h , i % & l v h q d e o h g t & & ' p x v w v w l o o e h p h w z k l f k z l o o f d x v h d j d s l q w k h g d w d r x w s x w d v v k r z q l q ) l j x u h 1 r q f r q v h f x w l y h 5 ( $ ' g d w d l v u h i o h f w h g l q ) l j x u h ' ' 5 6 ' 5 $ 0 v g r q r w d o o r z l q w h u u x s w l q j r u w u x q f d w l q j d q \ 5 ( $ ' e x u v w ' d w d i u r p d q \ 5 ( $ ' e x u v w p x v w e h f r p s o h w h g e h i r u h d v x e v h t x h q w : 5 , 7 ( e x u v w l v d o o r z h g $ q h [ d p s o h r i d 5 ( $ ' e x u v w i r o o r z h g e \ d : 5 , 7 ( e x u v w i r u % / l v v k r z q l q ) l j x u h 7 r h q v x u h w k h 5 ( $ ' g d w d l v f r p s o h w h g e h i r u h w k h : 5 , 7 ( g d w d l v r q w k h e x v w k h p l q l p x p 5 ( $ ' w r : 5 , 7 ( w l p l q j l v 5 / t & & ' y : / t & . logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read command at t0 and t4. 3. do n (or b) = data-out from column n (or column b). 4. bl8, rl = 5 (cl = 5, al = 0). t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 don t care transitioning data t12 t13 t14 t rpst nop d aer daer pon pon pon pon pon pon pon pon pon pon pon pon ck ck# c ommand 1 dq 3 dqs, dqs# bank, col n bank, co l b add ress 2 rl = 5 t rpre t ccd rl = 5 do n+ 3 do n+ 2 do n + 1 do n do n+ 7 do n + 6 do n + 5 do n+ 4 do b + 3 do b + 2 do b+ 1 do b do b + 7 do b + 6 do b + 5 do b+ 4 figure 60 - consecutive read bursts (bl8) logic devices incorporated www.logicdevices.com 108 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bc4 setting is activated by either mr0[1:0] = 10 or mr0[1:0] = 01 and a12 = 0 during read command at t0 and t4. 3. do n (or b) = data-out from column n (or column b). 4. bc4, rl = 5 (cl = 5, al = 0). nop ck ck# comman d 1 dq 3 dqs, dqs# t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 address 2 t10 t11 don t care transitioning data t12 t1 3t14 read read nop nop nop nop nop nop nop nop nop nop nop nop bank, col n bank, col b t rpst t rpre t rpst t rpre rl = 5 do n+ 3 do n + 2 do n + 1 do n do b+ 3 do b+ 2 do b+ 1 do b rl = 5 t ccd figure 61 - consecutive read bursts (bc4) logic devices incorporated www.logicdevices.com 109 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. al = 0, rl = 8. 2. do n (or b) = data-out from column n (or column b). 3. seven subsequent elements of data-out appear in the programmed order following do n. 4. seven subsequent elements of data-out appear in the programmed order following do b. don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 dqs, dqs# command nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop read nop read add ress bank a, co l n bank a, col b ck ck # dq do n do b c l = 8 c l = 8 figure 62 - nonconsecutive read bursts logic devices incorporated www.logicdevices.com 110 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the read command at t0, and the write command at t6. don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ck ck # command 1 nop nop nop nop nop write nop nop nop nop nop nop nop nop nop t wpst t rpre t wpre t rpst dqs, dqs# dq 3 wl = 5 t wr t wtr read do n do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 read-to-write command delay = rl + t ccd + 2 t ck - wl t bl = 4 clocks add ress 2 bank, col b bank, col n rl = 5 figure 63 - read (bl8) to write (bl8) logic devices incorporated www.logicdevices.com 111 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bc4 otf setting is activated by mr0[1:0] and a12 = 0 during read command at t0 and write command at t4. 3. do n = data-out from column n; di n = data-in from column b. 4. bc4, rl = 5 (al - 0, cl = 5), wl = 5 (al = 0, cwl = 5). don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ck ck# add ress 2 bank, col n bank, col b command 1 read nop nop nop write nop nop nop nop nop nop nop nop nop nop nop t wpst t wpre t rpst dqs, dqs# dq 3 wl = 5 read-to-write command delay = rl + t cc d/2 + 2 t ck - wl t wr t wtr t bl = 4 clo cks t rpre rl = 5 do n do n+ 1 do n+ 2 do n + 3 di n di n + 1 di n + 2 di n+ 3 figure 64 - read (bc4) to write (bc4) otf logic devices incorporated www.logicdevices.com 112 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the read command at t0, and the write command at t6. 3. do n = data-out from column, di b = data-in for column b. 4. bl8, rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ck ck # command 1 nop nop nop nop nop write nop nop nop nop nop nop nop nop nop t wpst t rpre t wpre t rpst dqs, dqs# dq 3 wl = 5 t wr t wtr read do n do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 read-to-write command delay = rl + t ccd + 2 t ck - wl t bl = 4 clocks add ress 2 bank, col b bank, col n rl = 5 figure 65 - read to precharge (bl8) logic devices incorporated www.logicdevices.com 113 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product ck ck# don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 command nop nop nop nop nop nop nop nop nop act nop nop nop nop nop read nop pre add ress bank a, col n bank a, (or all) bank a, row b t rp t rtp dqs, dqs# dq do n do n+ 1 do n+ 2 do n+ 3 t ras figure 66 - read to precharge (bc4) logic devices incorporated www.logicdevices.com 114 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product ck ck# command dq dqs, dqs# active n t0 t1 dont care nop nop t6 t12 nop read n t13 nop do n+ 3 do n + 2 do n + 1 rl = al + cl = 11 t14 nop do n t rcd (min) al = 5 cl = 6 t11 bc4 indicates a break in time scale transitioning data t2 nop figure 67 - read to precharge (al = 5, cl = 6) logic devices incorporated www.logicdevices.com 115 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product ck ck # command nop nop nop nop add ress dq dqs, dqs# don t care transitioning data nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ta0 t rtp (min) nop read nop al = 4 nop nop cl = 6 nop t ras (min) act indicates a break in time scale t rp bank a, col n bank a, row b do n do n+ 1 do n+ 2 do n+ 3 figure 68 - read with auto precharge (al = 4, cl = 6) logic devices incorporated www.logicdevices.com 116 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product $ ' 4 6 [ w r ' 4 r x w s x w w l p l q j l v v k r z q l q ) l j x u h 7 k h ' 4 w u d q v l w l r q v e h w z h h q y d o l g g d w d r x w s x w v p x v w e h z l w k l q t ' 4 6 4 r i w k h f u r v v l q j s r l q w r i / > 8 @ ' 4 6 [ / > 8 @ ' 4 6 [ ? ' 4 6 p x v w d o v r p d l q w d l q d p l q l p x p + , * + d q g / 2 : w l p h r i t 4 6 + d q g t 4 6 / 3 u l r u w r w k h 5 ( $ ' s u h d p e o h w k h ' 4 e d o o v z l o o h l w k h u e h i o r d w l q j r u w h u p l q d w h g g h s h q g l q j r q w k h v w d w x v r i w k h 2 ' 7 v l j q d o ) l j x u h v k r z v w k h v w u r e h w r f o r f n w l p l q j g x u l q j d 5 ( $ ' 7 k h f u r v v l q j s r l q w ' 4 6 [ ' 4 6 [ ? p x v w w u d q v l w l r q z l w k ? t ' 4 6 & . r i w k h f o r f n f u r v v l q j s r l q w 7 k h g d w d r x w k d v q r w l p l q j u h o d w l r q v k l s w r f o r f n r q o \ w r ' 4 6 d v v k r z q l q ) l j x u h ) l j x u h d o v r v k r z v w k h 5 ( $ ' s u h d p e o h d q g s r v w d p e o h 1 r u p d o o \ e r w k ' 4 6 [ d q g ' 4 6 [ ? d u h + , * + = w r v d y h s r z h u 9 dd 4 3 u l r u w r g d w d r x w s x w i u r p w k h 6 ' 5 $ 0 ' 4 6 [ l v g u l y h q / 2 : d q g ' 4 6 [ ? g u l y h q + , * + i r u t 5 3 5 ( 7 k l v l v n q r z q d v w k h 5 ( $ ' s u h d p e o h 7 k h 5 ( $ ' s r v w d p e o h t 5 3 6 7 l v r q h k d o i f o r f n i u r p w k h o d v w / > 8 @ ' 4 6 [ / > 8 @ ' 4 6 [ ? w u d q v l w l r q ' x u l q j w k h 5 ( $ ' s r v w d p e o h / > 8 @ ' 4 6 [ l v g u l y h q / 2 : d q g / > 8 @ ' 4 6 [ ? g u l y h q + , * + : k h q f r p s o h w h w k h ' 4 z l o o h l w k h u e h g l v d e o h g r u z l o o f r q w l q x h w h u p l q d w l q j g h s h q g l q j r q w k h v w d w h r i w k h 2 ' 7 v l j q d o ) l j x u h g h p r q - v w u d w h v k r z w r p h d v x u h t rpst. read logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1, 0] = 0, 0 or mr0[0, 1] = 0, 1 and a12 = 1 during read command at t0. 3. do n = data-out from column n. 4. bl8, rl = 5 (al = 0, cl = 5). 5. output timings are referenced to v cc q/2 and dll on and locked. 6. t dqsq defines the skew between dqs, dqs# to data and does not define dqs, dqs# to clock. 7. early data transitions may not always happen at the same dq. data transitions of a dq can vary (either early or late) within a burst. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 bank, col n t rpst nop read nop nop nop nop nop nop nop nop nop ck ck# command 1 add ress 2 t dqsq (max) dqs, dqs# dq 3 (last data valid) dq 3 (first data no lon ger valid) all dq collectively do n do n+ 3 do n + 2 do n+ 1 do n+ 7 do n+ 6 do n+ 5 do n+ 4 do n + 2 do n+ 1 do n+ 7 do n + 6 do n+ 5 do n+ 4 do n+ 3 do n+ 2 do n+ 1 do n do n+ 7 do n+ 6 do n+ 5 do n do n + 3 t rpre don t care transitioning data data valid data valid t qh t qh t hz (dq) max do n+ 4 rl = al + cl t dqsq (max) t lz (dq) min figure 69 - data output timing ? t dqsq and data valid window logic devices incorporated www.logicdevices.com 118 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t + = d q g t / = w u d q v l w l r q v r f f x u l q w k h v d p h d f f h v v w l p h d v y d o l g g d w d w u d q v l w l r q v 7 k h v h s d u d p h w h u v d u h u h i h u h q f h g w r d v s h f l i l f y r o w d j h o h y h o z k l f k v s h f l i l h v z k h q w k h g h y l f h r x w s x w l v q r o r q j h u g u l y l q j t + = ' 4 6 d q g t + = ' 4 r u e h j l q v g u l y l q j t / = ' 4 6 t / = ' 4 ) l j x u h v k r z v d p h w k r g w r f d o f x o d w h w k h s r l q w z k h q w k h g h y l f h l v q r w o r q j h u g u l y l q j t + = ' 4 6 d q g t + = ' 4 r u e h j l q v g u l y l q j t / = ' 4 6 t / = ' 4 e \ p h d v x u l q j w k h v l j q d o d w w z r g l i i h u h q w y r o w d j h v 7 k h d f w x d o y r o w d j h p h d v x u h p h q w s r l q w v d u h q r w f u l w l f d o d v o r q j d v w k h f d o f x o d w l r q l v f r q v l v w h q w 7 k h s d u d p h w h u v t / = ' 4 6 t / = ' 4 t + = ' 4 6 d q g t + = ' 4 d u h g h i l q h g d v v l q j o h h q g h g output timing logic devices incorporated www.logicdevices.com 119 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product rl measured to this point dqs, dqs# early strobe ck t dqsck (min) t lz (dqs) min t hz (dqs) min dqs, dqs# late strobe t dqsck (max) t lz (dqs) max t hz (dqs) max t dqsck (min) t dqsck (min) t dqsck (max) t dqsck (max) t dqsck (max) t dqsck (min) ck# t rpre t qsh t qsl t qsl t qsl t qsl t qsh t qsh t qsh bit 0 bit 1 bit 2 bit 7 t rpre bit 0 bit 1 bit 2 bit 7 bit 6 bit 3 bit 4 bit 5 bit 6 bit 4 bit 3 bit 5 t rpst t rpst t0 t1 t2 t3 t4 t5 t 6 figure 70 - data strobe timing ? reads logic devices incorporated www.logicdevices.com 120 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product notes: 1. within a burst, the rising strobe edge is not necessarily fixed at t dqsck (min) or t dqsck (max). instead, the rising strobe edge can vary between t dqsck (min) and t dqsck (max). 2. the dqs high pulse width is defined by t qsh, and the dqs low pulse width is defined by t qsl. likewise, t lz (dqs) min and t hz (dqs) min are not tied to t dqsck (min) (early strobe case) and t lz (dqs) max and t hz (dqs) max are not tied to t dqsck (max) (late strobe case); however, they tend to track one another. 3. the minimum pulse width of the read preamble is defined by t rpre (min). the minimum pulse width of the read postamble is defined by t rpst (min). t hz (dqs), t hz (dq) t hz (dqs), t hz (dq) end point = 2 t1 - t2 v oh - xmv v tt - xmv v ol + xmv v tt + xmv v oh - 2xmv v tt - 2xmv v ol + 2xmv v tt + 2xmv t lz (dqs), t lz (dq) t lz (dqs), t lz (dq) begin point = 2 t1 - t2 t1 t1 t2 t2 figure 71 - method for calculating t lz and t hz logic devices incorporated www.logicdevices.com 121 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 72 - t rpre t iming t rpre dqs - dqs# dqs dqs# t1 t rpre begins t2 t rpre ends ck ck # v tt resultin g differential signal relevant for t rpre specification t c t a t b t d 0v v tt v tt single-ended signal, provided as background information single-ended signal, provided as background information f igure 73 - t rpst t iming t rpst dqs - dqs# dqs dqs# t1 t rpst begins t2 t rpst ends resultin g differential signal relevant for t rpst specification ck ck # v tt t c t a t b t d single-ended signal, provided as background information 0v v tt v tt single-ended signal, provided as background information logic devices incorporated www.logicdevices.com 122 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 74 - t wpre t iming dqs - dqs# t1 t wpre begins t2 t wpre ends t wpre resulting differential signal relevant for t wpre specification 0v ck ck# v tt f igure 75 - t wpst t iming t wpst dqs - dqs# t1 t wpst begins t2 t wpst ends resulting differential signal relevant for t wpst specification 0v ck ck # v tt logic devices incorporated www.logicdevices.com 123 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product write : 5 , 7 ( e x u v w v d u h l q l w l d w h g z l w k d : 5 , 7 ( f r p p d q g 7 k h v w d u w l q j & 2 / 8 0 1 d q g % $ 1 . d g g u h v v h v d u h s u r y l g h g z l w k w k h : 5 , 7 ( f r p p d q g d q g $ 8 7 2 3 5 ( - & + $ 5 * ( l v v h o h f w h g w k h 5 2 : e h l q j d f f h v v h g z l o o e h 3 5 ( & + $ 5 * ( ' d w w k h h q g r i : 5 , 7 ( e x u v w , i $ 8 7 2 3 5 ( & + $ 5 * ( l v q r w v h o h f w h g w k h 5 2 : z l o o u h p d l q r s h q i r u v x e v h t x h q w d f f h v v h v $ i w h u d : 5 , 7 ( f r p p d q g k d v e h h q l v v x h g w k h : 5 , 7 ( e x u v w p d \ q r w e h l q w h u u x s w h g ) r u w k h j h q h u l f : 5 , 7 ( f r p p d q g v x v h g l q ) l j x u h w k r x j k ) l j x u h $ 8 7 2 3 5 ( & + $ 5 * ( l v g l v d e o h g ' x u l q j : 5 , 7 ( e x u v w v w k h i l u v w y d o l g g d w d l q h o h p h q w l v u h j l v w h u h g r q d u l v l q j h g j h r i ' 4 6 [ i r o o r z l q j w k h : 5 , 7 ( / $ 7 ( 1 & < : / f o r f n v o d w h u d q g v x e v h t x h q w g d w d h o h p h q w v z l o o e h u h j l v w h u h g r q v x f f h v v l y h h g j h v r i ' 4 6 [ : 5 , 7 ( / $ 7 ( 1 & < : / l v g h i l q h g d v w k h v x p r i 3 2 6 7 ( ' & $ 6 $ ' ' , 7 , 9 ( / $ 7 ( 1 & < $ / d q g & $ 6 : 5 , 7 ( / $ 7 ( 1 & < & : / : / $ / & : / 7 k h y d o x h v r i $ / d q g & : / d u h s u r j u d p p h g l q w k h 0 5 d q g 0 5 u h j l v w h u v u h v s h f w l y h o \ 3 u l r u w r w k h i l u v w y d o l g ' 4 6 [ h g j h d i x o o f \ f o h l v q h h g h g l q f o x g l q j d g x p p \ f u r v v r y h u r i ' 4 6 [ ' 4 6 [ ? d q g v s h f l i l h g d v w k h : 5 , 7 ( s u h d p e o h v k r z q l q ) l j x u h 7 k h k d o i f \ f o h r q ' 4 6 [ i r o o r z l q j w k h o d v w g d w d l q h o h p h q w l v n q r z q d v w k h : 5 , 7 ( s r v w d p e o h 7 k h w l p h e h w z h h q w k h : 5 , 7 ( f r p p d q g d q g w k h i l u v w y d o l g h g j h r i ' 4 6 [ l v : / f o r f n v ? t ' 4 6 6 ) l j x u h w k u r x j k ) l j x u h v k r z w k h q r p l q d o f d v h z k h u h t ' 4 6 6 q v k r z h y h u ) l j x u h l q f o x g h v t ' 4 6 6 0 , 1 d q g t ' 4 6 6 0 $ ; f d v h v ' d w d p d \ e h p d v n h g i u r p f r p s o h w l q j d : 5 , 7 ( x v l q j g d w d p d v n 7 k h p d v n r f f x u v r q w k h ' 0 e d o o d o l j q h g w r w k h : 5 , 7 ( g d w d , i ' 0 l v / 2 : w k h : 5 , 7 ( f r p s o h w h v q r u p d o o \ , i ' 0 l v + , * + w k d w e l w r i g d w d l v p d v n h g 8 s r q f r p s o h w l r q r i d e x u v w d v v x p l q j q r r w k h u f r p p d q g v k d y h e h h q l q l w l d w h g w k h ' 4 z l o o u h p d l q + , * + = d q g d q \ d g g l w l r q d o l q s x w g d w d z l o o e h l j q r u h g ' d w d i r u d q \ : 5 , 7 ( e x u v w p d \ e h f r q f d w h q d w h g z l w k d v x e v h t x h q w : 5 , 7 ( f r p p d q g w r s u r y l g h d f r q w l q x r x v i o r z r i l q s x w g d w d 7 k h q h z : 5 , 7 ( f r p p d q g f d q e h t & & ' f o r f n v i r o o r z l q j w k h s u h y l r x v : 5 , 7 ( f r p p d q g 7 k h i l u v w g d w d h o h p h q w i u r p w k h q h z e x u v w l v d s s o l h g d i w h u w k h o d v w h o h p h q w r i d f r p s o h w h g e x u v w ) l j x u h v d q g v k r z f r q f d w h q d w h g e x u v w v $ q h [ d p s o h r i q r q f r q v h f x w l y h : 5 , 7 ( 6 l v v k r z q l q ) l j x u h ' d w d i r u d q \ : 5 , 7 ( e x u v w p d \ e h i r o o r z h g e \ d v x e v h t x h q w 5 ( $ ' f r p p d q g d i w h u t : 7 5 k d v e h h q p h w v h h ) l j x u h v d q g ' d w d i r u d q \ : 5 , 7 ( e x u v w p d \ e h i r o o r z h g e \ d v x e v h t x h q w 3 5 ( & + $ 5 * ( f r p p d q g s u r y l g l q j t : 5 k d v e h h q p h w d v v k r z q l q ) l j x u h d q g ) l j x u h both t : 7 5 d q g t : 5 v w d u w l q j w l p h p d \ y d u \ g h s h q g l q j r q w k h p r g h u h j l v w h u v h w w l q j v i l [ h g % & % / y v 2 7 ) logic devices incorporated www.logicdevices.com 124 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 76 - w rite b urst notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the write command at t0. 3. di n = data-in for column n. 4. bl8, wl = 5 (al = 0, cwl = 5). 5. t dqss must be met at each rising clock edge. 6. t wpst is usually depicted as ending at the crossing of dqs, dqs#; however, t wpst actually ends when dqs no longer drives low and dqs# no longer drives high. di n + 3 di n + 2 di n + 1 di n t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 don t care transitioning data di n + 7 di n + 6 di n + 5 di n + 4 bank, col n nop write nop nop nop nop nop nop nop nop nop ck ck# c ommand 1 dq 3 dqs, dqs# add ress 2 t wpst t wpre t wpst t dqsl dq 3 dq 3 t wpst dqs, dqs# dqs, dqs# t dqsl t wpre t dqss t dqss t dsh t dsh t dsh t dsh t dss t dss t dss t dss t dss t dss t dss t dss t dss t dss t dsh t dsh t dsh t dsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh t dqsl t dqsl t dqsl t dqsl t dqsh t dqsh t dqsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh wl = al + cwl t dqss (min) t dqss (nom) t dqss (max) t dqsl t wpre di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 logic devices incorporated www.logicdevices.com 125 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 77 - c onsecutive write (bl8) to write (bl8) notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the write commands at t0 and t4. 3. di n (or b) = data-in for column n (or column b). 4. bl8, wl = 5 (al = 0, cwl = 5). wl = 5 wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ccd t wpre t10 t11 don t care transitioning data t12 t13 t14 valid valid nop write write nop nop nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 3 dqs, dqs# add ress 2 t wpst t wr t wtr t bl = 4 clocks di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 f igure 78 - c onsecutive write (bc4) to write (bc4) via mrs or otf notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bc4, wl = 5 (al = 0, cwl = 5). 3. di n (or b) = data-in for column n (or column b). 4. the bc4 setting is activated by mr0[1:0] = 01 and a12 = 0 during the write command at t0 and t4. wl = 5 wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ccd t wpre t10 t11 don t care transitioning data t12 t13 t14 vali d vali d nop write write nop nop nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 3 dqs, dqs# address 2 t wpst t wr t wtr t wpst t wpre di n + 3 di n + 2 di n + 1 di n di b + 3 di b + 2 di b + 1 di b t bl = 4 clo cks logic devices incorporated www.logicdevices.com 126 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 79 - n onconsecutive write to write notes: 1. di n (or b) = data-in for column n (or column b). 2. seven subsequent elements of data-in are applied in the programmed order following do n. 3. each write command may be to any bank. 4. shown for wl = 7 (cwl = 7, al = 0). ck ck# c ommand nop nop nop add ress dq dm dqs, dqs# transitioning data nop nop nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 nop write nop write vali d vali d nop di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 don't care di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 wl = c wl + al = 7 wl = c wl + al = 7 f igure 80 - write (bl8) to read (bl8) notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to the same device and starts with the first rising clock edge after the last write data shown at t9. 3. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and mr0[12] = 1 during the write command at t0. the read command at ta0 can be either bc4 or bl8, depending on mr0[1:0] and the a12 status at ta0. 4. di n = data-in for column n. 5. rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t wpre t10 t11 don t care transitioning data ta0 nop write read vali d vali d nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 4 dqs, dqs# add ress 3 t wpst t wtr 2 indicates a break in time scale di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 81 - write to read (bc4 m ode r egister s etting ) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to the same device and starts with the first rising clock edge after the last write data shown at t7. 3. the fixed bc4 setting is activated by mr0[1:0] = 10 during the write command at t0 and the read command at ta0. 4. di n = data-in for column n. 5. bc4 (fixed), wl = 5 (al = 0, cwl = 5), rl = 5 (al = 0, cl = 5). wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ta0 don t care transitioning data nop write vali d read vali d pon pon pon pon pon pon pon nop ck ck# command 1 dq 4 dqs, dqs# add ress 3 t wpst t wtr 2 t wpre indicates a break in time scale di n + 3 di n + 2 di n + 1 di n logic devices incorporated www.logicdevices.com 128 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 82 - write (bc4 otf) to read (bc4 otf) notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. t wtr controls the write-to -read delay to the same device and starts after t bl. 3. the bc4 otf setting is activated by mr0[1:0] = 01 and a 12 = 0 during the write command at t0 and the read command at tn. 4. di n = data-in for column n. 5. bc4, rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). wl = 5 rl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t wpre t10 t11 don t care transitioning data tn nop write read vali d vali d nop nop nop nop nop nop nop nop nop ck ck# c ommand 1 dq 4 dqs, dqs# add ress 3 t wpst t bl = 4 clo cks nop t wtr 2 indicates a break in time scale di n + 3 di n + 2 di n + 1 di n logic devices incorporated www.logicdevices.com 129 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 83 - write (bl8) to precharge notes: 1. di n = data-in from column n. 2. seven subsequent elements of data-in are applie d in the programmed order following do n. 3. shown for wl = 7 (al = 0, cwl = 7). t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 ta0 ta1 di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 nop write vali d nop nop nop nop nop nop nop nop nop nop nop nop pre ck ck # c ommand dq bl8 dqs, dqs# add ress don t care transitioning data indicates a break in time scale t wr wl = al + cwl vali d f igure 84 - write (bc4 m ode r egister s etting ) to precharge notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the write recovery time ( t wr) is referenced from the first rising clock edge after the last write data is shown at t7. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. 3. the fixed bc4 setting is activated by mr0[ 1:0] = 10 during the write command at t0. 4. di n = data-in for column n. 5. bc4 (fixed), wl = 5, rl = 5. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 ta0 ta1 di n + 3 di n + 2 di n + 1 di n nop write vali d nop nop nop nop nop nop nop nop nop nop nop nop pre ck ck # comman d dq bc4 dqs, dqs# add ress don t care transitioning data indicates a break in time scale t wr wl = al + cwl vali d logic devices incorporated www.logicdevices.com 130 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 85 - write (bc4 otf) to precharge notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the write recovery time ( t wr) is referenced from the rising clock edge at t9. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. 3. the bc4 setting is activated by mr0[1:0] = 01 and a12 = 0 during the write command at t0. 4. di n = data-in for column n. 5. bc4 (otf), wl = 5, rl = 5. wl = 5 t0 t1 t2 t3 t4 t 5 t6 t 7 t8 t9 t n don t care transitioning data bank, col n nop write pre nop nop nop nop nop nop nop nop ck ck# command 1 dq 4 dqs, dqs # add ress 3 t wpst t wpre indicates a break in time scale di n + 3 di n + 2 di n + 1 di n t wr 2 valid dq input timing f igure 86 - d ata i nput t iming t dh t ds dm dq di b dq s, dqs# don t care transitioning data t dqsh t dqsl t wpre t wpst p h p r u \ f r q w u r o o h u d i w h u w k h o d v w g d w d l v z u l w w h q w r w k h 6 ' 5 $ 0 g x u l q j w k h : 5 , 7 ( s r v w d p e o h t : 3 6 7 ' d w d v h w x s d q g k r o g w l p h v d u h v k r z q l q ) l j x u h $ o o v h w x s d q g k r o g w l p h v d u h p h d v x u h g i u r p w k h f u r v v l q j s r l q w v r i ' 4 6 [ d q g ' 4 6 [ ? 7 k h v h v h w x s d q g k r o g y d o x h v s h u w d l q w r g d w d l q s x w d q g g d w d p d v n l q s x w $ g g l w l r q d o o \ w k h k d o i s h u l r g r i w k h g d w d l q s x w v w u r e h l v v s h f l i l h g e \ t ' 4 6 + and t dqsl. ) l j x u h v k r z v w k h v w u r e h w r f o r f n w l p l q j g x u l q j d : 5 , 7 ( ' 4 6 [ ' 4 6 [ ? p x v w w u d q v l w l r q z l w k l q t & . r i w k h f o r f n w u d q v l w l r q v d v o l p l w h g e \ t dqss. $ o o g d w d d q g g d w d p d v n v h w x s d q g k r o g w l p l q j v d u h p h d v x u h g u h o d w l y h w r w k h ' 4 6 [ ' 4 6 [ ? f u r v v l q j v q r w w k h f o r f n f u r v v l q j 7 k h : 5 , 7 ( s u h d p e o h d q g s r v w d p e o h d u h d o v r v k r z q 2 q h f o r f n s u l r u w r g d w d l q s x w w r w k h 6 ' 5 $ 0 ' 4 6 [ p x v w e h + , * + d q g ' 4 6 [ ? p x v w e h / 2 : 7 k h q i r u d k d o i f o r f n ' 4 6 [ l v g u l y h q / 2 : ' 4 6 [ ? l v g u l y h q + , * + g x u l q j w k h : 5 , 7 ( s u h d p e o h t : 3 5 ( o l n h z l v h ' 4 6 [ p x v w e h n h s w / 2 : e \ w k h logic devices incorporated www.logicdevices.com 131 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product precharge , q s x w $ g h w h u p l q h v z k h w k h u r q h e d q n r u d o o e d q n v d u h w r e h 3 5 ( & + $ 5 * ( ' d q g l q w k h f d v h z k h u h r q o \ r q h e d q n l v w r e h s u h f k d u j h g l q s x w v % $ > @ v h o h f w w k h d u u d \ % $ 1 . : k h q d o o e d q n v d u h w r e h 3 5 ( & + $ 5 * ( ' l q s x w v % $ > @ d u h w u h d w h g d v v ' r q u w & d u h w $ i w h u d e d q n l v 3 5 ( & + $ 5 * ( ' l w l v l q w k h , ' / ( 6 w d w h d q g p x v w e h $ & 7 , 9 $ 7 ( ' s u l r u w r d q \ 5 ( $ ' r u : 5 , 7 ( f r p p d q g v e h l q j l v v x h g self refresh 7 k h 6 ( / ) 5 ( ) 5 ( 6 + f r p p d q g l v l q l w l d w h g o l n h d 5 ( ) 5 ( 6 + f r p p d q g h [ f h s w & . ( l v / 2 : 7 k h ' / / l v d x w r p d w l f d o o \ g l v d e o h g x s r q h q w h u l q j 6 ( / ) 5 ( ) 5 ( 6 + d q g l v d x w r p d w l f d o o \ h q d e o h g d q g u h v h w x s r q h [ l w l q j 6 ( / ) 5 ( ) 5 ( 6 + $ o o s r z h u v x s s o \ l q s x w v l q f o x g l q j 9 5 ( ) & $ d q g 9 5 ( ) ' 4 p x v w e h p d l q w d l q h g d w y d o l g o h y h o v x s r q h q w u \ h [ l w d q g g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h r s h u d w l r q 9 5 ( ) ' 4 p d \ i o r d w r u q r w g u l y h 9 dd 4 z k l o h l q w k h 6 ( / ) 5 ( ) 5 ( 6 + p r g h x q g h u f h u w d l q f r q g l w l r q v x 9 v v 9 5 ( ) ' 4 9 dd l v p d l q w d l q h g x 9 5 ( ) ' 4 l v y d o l g d q g v w d e o h s u l r u w r & . ( j r l q j e d f n + , * + x 7 k h i l u v w : 5 , 7 ( r s h u d w l r q p d \ q r w r f f x u h d u o l h u w k d q f o r f n v d i w h u 9 5 ( ) ' 4 is valid x $ o o r w k h u 6 ( / ) 5 ( ) 5 ( 6 + p r g h h [ l w w l p l q j u h t x l u h p h q w v d u h p h w 7 k h 6 ' 5 $ 0 p x v w e h l g o h z l w k d o o % $ 1 . 6 l q w k h 3 5 ( & + $ 5 * ( v w d w h t 5 3 l v v d w l v i l h g d q g q r e x u v w v d u h l q s u r j u h v v e h i r u h d 6 ( / ) 5 ( ) 5 ( 6 + h q w u \ f r p p d q g f d q e h l v v x h g 2 ' 7 p x v w d o v r e h w x u q h g r i i e h i r u h 6 ( / ) 5 ( ) 5 ( 6 + h q w u \ e \ u h j l v w h u l q j w k h 2 ' 7 e d o o / 2 : s u l r u w r w k h 6 ( / ) 5 ( ) 5 ( 6 + h q w u \ f r p p d q g v h h v 2 q ' l h 7 h u p l q d w l r q 2 ' 7 i r u w l p l q j u h t x l u h p h q w v , i 5 tt _nom and r tt b : 5 d u h g l v d e o h g l q w k h p r g h u h j l v w h u v 2 ' 7 f d q e h d v ' r q u w & d u h w $ i w h u w k h 6 ( / ) 5 ( ) 5 ( 6 + h q w u \ f r p p d q g l v u h j l v w h u h g & . ( p x v w e h k h o g / 2 : w r n h h s w k h 6 ' 5 $ 0 l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h $ i w h u w k h 6 ' 5 $ 0 k d v h q w h u h g 6 ( / ) 5 ( ) 5 ( 6 + p r g h d o o h [ w h u q d o f r q w u r o v l j q d o v h [ f h s w & . ( d q g 5 ( 6 ( 7 ? e h f r p h v ' r q u w & d u h w 7 k h 6 ' 5 $ 0 l q l w l d w h v d p l q l p x p r i r q h 5 ( ) 5 ( 6 + f r p p d q g l q w h u q d o o \ z l w k l q w k h t & . ( s h u l r g z k h q l w h q w h u v 6 ( / ) 5 ( ) 5 ( 6 + p r g h 7 k h u h t x l u h p h q w v i r u h q w h u l q j d q g h [ l w l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h g h s h q g r q w k h v w d w h r i w k h f o r f n g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h ) l u v w d q g i r u h p r v w w k h f o r f n p x v w e h v w d e o h p h h w l q j t & . v s h f l i l f d w l r q v z k h q 6 ( / ) 5 ( ) 5 ( 6 + p r g h l v h q w h u h g , i w k h f o r f n u h p d l q v v w d e o h d q g w k h i u h t x h q f \ l q q r w d o w h u h g z k l o h l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h w k h q w k h 6 ' 5 $ 0 l v d o o r z h g w r h [ l w 6 ( / ) 5 ( ) 5 ( 6 + d i w h u t & . ( 6 5 l v v d w l v i l h g & . ( l v d o o r z h g w r w u d q v l w l r q + , * + t & . ( 6 5 o d w h u w k d q z k h q & . ( z d v u h j l v w h u h g / 2 : 6 l q f h w k h f o r f n u h p d l q v v w d e o h l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h q r i u h t x h q f \ f k d q j h t & . 6 5 ( d q g t & . 6 5 ; d u h q r w u h t x l u h g + r z h y h u l i w k h f o r f n l v d o w h u h g g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h w k h q t & . 6 5 ( d q g t & . 6 5 ; p x v w e h v d w l v i l h g : k h q h q w h u l q j 6 ( / ) 5 ( ) 5 ( 6 + t & . 6 5 ( p x v w e h v d w l v i l h g s u l r u w r d o w h u l q j w k h f o r f n u v i u h t x h q f \ 3 u l r u w r h [ l w l q j 6 ( / ) 5 ( ) 5 ( 6 + t & . 6 5 ; p x v w e h v d w l v i l h g s u l r u w r u h j l v w h u l q j & . ( + , * + : k h q & . ( l v + , * + g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + h [ l w 1 2 3 r u ' ( 6 p x v w e h l v v x h g i r u t ; 6 w l p h t ; 6 l v u h t x l u h g i r u w k h f r p s o h w l r q r i d q \ l q w h u q d o 5 ( ) 5 ( 6 + w k d w l v d o u h d g \ l q s u r j u h v v d q g p x v w e h v d w l v i l h g e h i r u h d y d o l g f r p p d q g q r w u h t x l u l q j d o r f n h g ' / / f d q e h l v v x h g w r w k h g h y l f h t ; 6 l v d o v r w k h h d u o l h v w w l p h w k d w d 6 ( / ) 5 ( ) 5 ( 6 + u h h q w u \ p d \ r f f x u v h h ) l j x u h % h i r u h d f r p p d q g u h t x l u l q j d o r f n h g ' / / f d q e h d s s o l h g d = 4 & / f r p p d q g p x v w e h l v v x h g t = 4 2 3 ( 5 w l p l q j p x v w e h p h w d q g t ; 6 ' / / p x v w e h v d w l v i l h g 2 ' 7 p x v w e h r i i g x u l q j t ; 6 ' / / logic devices incorporated www.logicdevices.com 132 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 87 - s elf r efresh e ntry /e xit t iming notes: 1. the clock must be valid and stable meeting t ck specifications at least t cksre after entering self refresh mode, and at least t cksrx prior to exiting self refresh mode, if the clock is stopped or altered between states ta0 and tb0. if the clock remains valid and unchanged from entry and during self refresh mode, then t cksre and t cksrx do not apply; however, t ckesr must be satisfied prior to exiting at srx. 2. odt must be disabled and r tt off prior to entering self re fresh at state t1. if both r tt _ nom and r tt _ wr are disabled in the mode registers, odt can be a dont care. 3. self refresh entry (sre) is synchronous via a refresh command with cke low. 4. a nop or des command is required at t2 after the sre command is issued prior to the inputs becoming dont care. 5. nop or des commands are required prior to exiting self refresh mode until state te0. 6. t xs is required before any commands not requiring a locked dll. 7. t xsdll is required before any commands requiring a locked dll. 8. the device must be in the all banks idle state prior to entering self refresh mode. for exam- ple, all banks must be precharged, t rp must be met, and no data bursts can be in progress. 9. self refresh exit is asynchronous; however, t xs and t xsdll timings start at the first rising clock edge where cke high satisfies t isxr at tc1. t cksrx timing is also measured so that t isxr is satisfied at tc1. ck ck # command nop nop 4 sre(ref) 3 add ress ck e odt 2 reset# 2 vali d vali d 6 srx (nop) nop 5 t rp 8 t xs 6 , 9 t xs dll 7, 9 odtl t is t cpded t is t is enter self refresh mode (synchronous) exit self refresh mode (asynchronous) t0 t1 t2 tc 0 tc1 td0 tb 0 don t care te0 vali d vali d 7 vali d vali d vali d t ih ta0 tf0 indicates a break in time scale t cksrx 1 t cksre 1 t ckesr (min) 1 logic devices incorporated www.logicdevices.com 133 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 6 h o i 5 h i u h v k 7 h p s h u d w x u h 6 5 7 extended temperature usage / 2 * , & ' h y l f h v , q f l 0 2 ' ' ' 5 6 ' 5 $ 0 p r g x o h v x s s r u w v w k h r s w l r q d o h [ w h q g h g w h p s h u d w x u h u d q j h x s w r d ? & z k l o h v x s s r u w l q j 6 ( / ) 5 ( ) 5 ( 6 + $ 8 7 2 5 ( ) 5 ( 6 + d q g v x s s r u w 7 $ w h p s h u d w x u h v ! ? & d ? & z l w k 0 $ 1 8 $ / 5 ( ) 5 ( 6 + r q o \ : k h q x v l q j 6 ( / ) 5 ( ) 5 ( 6 + $ 8 7 2 5 ( ) 5 ( 6 + d q g w k h d p e l h q w w h p s h u d w x u h l v ! ? & 6 5 7 d q g $ 6 5 r s w l r q v p x v w e h x v h g 7 k h h [ w h q g h g u d q j h w h p s h u d w x u h u d q j h 6 ' 5 $ 0 p x v w e h 5 ( ) 5 ( 6 + ( ' h [ w h u q d o o \ d w ; d q \ w l p h w k h d p e l h q w w h p s h u d w x u h l v ! ? & 7 k h h [ w h u q d o 5 ( ) 5 ( 6 +- , 1 * u h t x l u h p h q w l v d f f r p s o l v k h g e \ u h g x f l q j w k h 5 ( ) 5 ( 6 + 3 ( 5 , 2 ' i u r p p v w r p v 6 ( / ) 5 ( ) 5 ( 6 + p r g h u h t x l u h v w k h x v h r i $ 6 5 r u 6 5 7 w r v x s s r u w w k h h [ w h q g h g w h p s h u d w x u h field mr2 bits description srt asr t able 63: self refresh t emperature and auto self refresh d escription , i $ 6 5 l v g l v d e o h g 0 5 > @ 6 5 7 p x v w e h s u r j u d p p h g w r l q g l f d w h t 2 3 ( 5 g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + 0 5 > @ 1 r u p d o r s h u d w l q j w h p s h u d w x u h u d q j h ? & w r d 85 ? & 0 5 > @ ( [ w h q g h g r s h u d w l q j w h p s h u d w x u h u d q j h ! ? & w r d 105 ? & , i $ 6 5 l v h q d e o h g 0 5 > @ 6 5 7 p x v w e h v h w w r h y h q l i w k h h [ w h q g h g w h p s h u d w x u h u d q j h l v v x s s r u w h g 0 5 > @ 6 5 7 l v g l v d e o h g : k h q $ 6 5 l v h q d e o h g w k h 6 ' 5 $ 0 d x w r p d w l f d o o \ s u r y l g h v 6 ( / ) 5 ( ) 5 ( 6 + s r z h u p d q d j h p h q w i x q f w l r q v u h i u h v k u d w h i r u d o o v x s s r u w h g r s h u d w l q j w h p s h u d w x u h y d o x h v 0 5 > @ $ 6 5 l v h q d e o h g 0 p x v w : k h q $ 6 5 l v q r w h q d e o h g w k h 6 5 7 e l w p x v w e h s u r j u d p p h g w r l q g l f d w h t 2 3 ( 5 g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + r s h u d w l r q 0 5 > @ $ 6 5 l v g l v d e o h g p x v w x v h p d q x d o 6 ( / ) 5 ( ) 5 ( 6 + 6 5 7 6 $ x w r 6 h o i 5 h i u h v k $ 6 5 self refresh operation 0 0 1 1 t able 64: self refresh m ode s ummary 6 ( / ) 5 ( ) 5 ( 6 + 0 r g h l v v x s s r u w h g l q w k h q r u p d o w h p s h u d w x u h u d q j h 6 ( / ) 5 ( ) 5 ( 6 + 0 r g h l v v x s s r u w h g l q q r u p d o d q g h [ w h q g h g d 95 ? & 0 $ ; w h p s h u d w x u h u d q j h v : k h q 6 5 7 l v h q d e o h g l w l q f u h d v h v v h o i u h i u h v k s r z h u f r q v x p s w l r q 6 h o i u h i u h v k p r g h l v v x s s r u w h g l q q r u p d o d q g h [ w h q g h g w h p s h u d w x u h u d q j h v 6 h o i u h i u h v k s r z h u f r q v x p s w l r q p d \ e h w h p s h u d w x u h g h s h q g h q w illegal. 0 1 0 1 permitted operating temperature range for self refresh mode mr2[7] (srt) mr2[6] (asr) 1 r u p d o ? & w r ? & 1 r u p d o d q g h [ w h q g h g ? & w r ? & 1 r u p d o d q g h [ w h q g h g ? & w r ? & power-down mode 3 r z h u g r z q l v v \ q f k u r q r x v o \ h q w h u h g z k h q & . ( l v u h j l v w h u h g / 2 : f r l q f l g h q w z l w k d 1 2 3 r u ' ( 6 f r p p d q g & . ( l v q r w d o o r z h g w r j r / 2 : z k l o h h l w k h u d q 0 5 6 0 3 5 = 4 & $ / 5 ( $ ' r u : 5 , 7 ( r s h u d w l r q l v l q s u r j u h v v & . ( l v d o o r z h g w r j r / 2 : z k l o h d q \ r i w k h r w k h u o h j d o r s h u d w l r q v d u h l q s u r j u h v v + r z h y h u w k h 3 2 : ( 5 ' 2 : 1 , dd v s h f l i l f d w l r q v d u h q r w d s s o l f d e o h x q w l o v x f k r s h u d w l r q v k d y h e h h q f r p s o h w h g ' h s h q g l q j r q w k h s u h y l r x v 6 ' 5 $ 0 v w d w h d q g w k h f r p p d q g l v v x h g s u l r u w r & . ( j r l q j / 2 : f h u w d l q w l p l q j f r q v w u d l q w v p x v w e h v d w l v i l h g d v q r w h g l q 7 d e o h 7 l p l q j g l d j u d p v g h w d l o l q j w k h g l i i h u h q w 3 2 : ( 5 ' 2 : 1 p r g h h q w u \ d q g h [ l w v d u h v k r z q l q ) l j x u h w k u r x j k ) l j x u h logic devices incorporated www.logicdevices.com 134 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product idle or active idle or active active active active active active idle power-down idle t able 65: command to power-down e ntry p arameters t $ & 7 3 ' ( 1 t 3 5 3 ' ( 1 t 5 ' 3 ' ( 1 t : 5 3 ' ( 1 t : 5 $ 3 ' ( 1 t 5 ( ) 3 ' ( 1 t ; 3 ' / / t 0 5 6 3 ' ( 1 $ & 7 , 9 $ 7 ( 3 5 ( & + $ 5 * ( 5 ( $ ' r u 5 ( $ ' $ 3 : 5 , 7 ( % / 2 7 ) % / 0 5 6 % & 2 7 ) : 5 , 7 ( % & 0 5 6 : 5 , 7 ( $ 3 % / 2 7 ) % / 0 5 6 % & 2 7 ) : 5 , 7 ( $ 3 % & 0 5 6 5 ( ) 5 ( 6 + 5 ( ) 5 ( 6 + 0 2 ' ( 5 ( * , 6 7 ( 5 6 ( 7 last command prior to cke low 1 1 t & . 1 t & . rl = 4 t & . t & . : / t & . t : 5 t & . : / t & . t : 5 t & . : / t & . : 5 t & . : / t & . : 5 t & . 1 t & . * u h d w h u r i t & . r u q v t mod figure 95 figure 96 figure 91 figure 92 figure 92 figure 93 figure 93 figure 94 figure 98 ) l j x u h sdram status parameter (min) parameter value figure ( q w h u l q j 3 2 : ( 5 ' 2 : 1 p r g h g l v d e o h v w k h l q s x w d q g r x w s x w e x i i h u v h [ f o x g l q j & . & . ? 2 ' 7 & . ( d q g 5 ( 6 ( 7 ? 1 2 3 r u ' ( 6 f r p p d q g v d u h u h t x l u h g x q w l o t & 3 ' ( ' k d v e h h q v d w l v i l h g d w z k l f k w l p h d o o v s h f l i l h g l q s x w r x w s x w e x i i h u v z l o o e h g l v d e o h g 7 k h ' / / v k r x o g e h l q d o r f n h g v w d w h z k h q 3 2 : ( 5 ' 2 : 1 l v h q w h u h g i r u w k h i d v w h v w p r g h w l p l q j , i w k h ' / / l v q r w o r f n h g g x u l q j w k h 3 2 : ( 5 ' 2 : 1 h q w u \ w k h ' / / p x v w e h u h v h w d i w h u h [ l w l q j 3 2 : ( 5 ' 2 : 1 i r u s u r s h u 5 ( $ ' r s h u d w l r q d v z h o o d v v \ q f k u r q r x v 2 ' 7 r s h u d w l r q ' x u l q j 3 2 : ( 5 ' 2 : 1 h q w u \ l i d q \ e d q n u h p d l q v r s h q d i w h u d o o l q s u r j u h v v f r p p d q g v d u h f r p s o h w h w k h 6 ' 5 $ 0 z l o o e h l q $ & 7 , 9 ( 3 2 : ( 5 ' 2 : 1 , i d o o e d q n v d u h f o r v h g d i w h u d o o l q s u r j u h v v f r p p d q g v d u h f r p s o h w h w k h 6 ' 5 $ 0 z l o o e h l q 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h r u i d v w ( ; , 7 p r g h : k h q h q w h u l q j 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 w k h ' / / l v w x u q h g r i i l q v o r z h [ l w p r g h r u n h s w r q l q i d v w ( ; , 7 p r g h 7 k h ' / / u h p d l q v r q z k h q h q w h u l q j $ & 7 , 9 ( 3 2 : ( 5 ' 2 : 1 d v z h o o 2 ' 7 k d v v s h f l d o w l p l q j f r q v w u d l q w v z k h q v o r z ( ; , 7 p r g h 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 l v h q d e o h g d q g h q w h u h g 5 h i h u w r v $ v \ q f k u r q r x v 2 ' 7 0 r g h w i r u g h w d l o h g 2 ' 7 x v d j h u h t x l u h p h q w v l q v o r z ( ; , 7 p r g h 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 $ v x p p d u \ r i w k h w z r 3 2 : ( 5 ' 2 : 1 p r g h v l v o l v w h g l q 7 d e o h : k l o h l q h l w k h u 3 2 : ( 5 ' 2 : 1 v w d w h & . ( l v k h o g / 2 : 5 ( 6 ( 7 ? l v k h o g + , * + d q g d v w d e o h f o r f n v l j q d o p x v w e h p d l q w d l q h g 2 ' 7 p x v w e h l q d y d o l g v w d w h e x w d o o r w k h u l q s x w v l j q d o v d u h d v ' r q u w & d u h w , i 5 ( 6 ( 7 ? j r h v / 2 : g x u l q j 3 2 : ( 5 ' 2 : 1 w k h 6 ' 5 $ 0 z l o o v z l w f k r x w r i 3 2 : ( 5 ' 2 : 1 d q g j r l q w r w k h 5 ( 6 ( 7 v w d w h $ i w h u & . ( l v u h j l v w h u h g / 2 : & . ( p x v w u h p d l q / 2 : x q w l o t 3 ' 0 , 1 k d v e h h q v d w l v i l h g 7 k h p d [ l p x p w l p h d o o r z h g i r u 3 2 : ( 5 ' 2 : 1 g x u d w l r q l v t 3 ' 0 $ ; [ w 5 ( ) , 7 k h 3 2 : ( 5 ' 2 : 1 v w d w h v d u h v \ q f k u r q r x v o \ h [ l w h g z k h q & . ( l v u h j l v w h u h g + , * + z l w k d u h t x l u h g 1 2 3 r u ' ( 6 f r p p d q g & . ( p x v w e h p d l q w d l q h g + , * + until t & . ( k d v e h h q v d w l v i l h g $ y d o l g h [ h f x w d e o h f r p p d q g p d \ e h d s s o l h g d i w h u 3 2 : ( 5 ' 2 : 1 ( ; , 7 / $ 7 ( 1 & < t ; 3 t ; 3 ' / / k d y h e h h q v d w l v i l h g $ v x p - p d u \ r i w k h 3 2 : ( 5 ' 2 : 1 p r g h v l v o l v w h g l q 7 d e o h d l l s t a t e $ & 7 , 9 ( d q \ e d q n r s h q 3 5 ( & + $ 5 * ( d o o e d q n v 3 5 ( & + $ 5 * ( ' t able 66: power-down m odes on on off relevant parameters mr1[12] t ; 3 w r d q \ r w k h u y d o l g & 2 0 0 $ 1 ' t ; 3 w r d q \ r w k h u y d o l g & 2 0 0 $ 1 ' t ; ' / / w r & 2 0 0 $ 1 ' 6 w k d w u h t x l u h w k h ' / / w r e h o r f n h g 5 ( $ ' 5 ' $ 3 2 ' 7 2 1 t ; 3 w r d q \ r w k h u y d o l g & 2 0 0 $ 1 ' sdram state v ' r q u w & d u h w 1 0 ) $ 6 7 ) $ 6 7 6 / 2 : power-down exit logic devices incorporated www.logicdevices.com 135 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 88 - a ctive p ower -d own e ntry and e xit ck ck# command nop nop nop nop address cke t ck t ch t cl enter power-down mode exit power-down mode dont care valid valid valid t cpded valid t is t ih t ih t is t0 t1 t2 ta0 ta1 ta2 ta3 ta4 nop t xp t cke (min) indicates a break in time scale t pd f igure 89 - p recharge p ower -d own (f ast -e xit m ode ) e ntry and e xit tckemin tckemin ck ck# pon pon pon pon dnammoc cke t ck t ch t cl enter power-down mode exit power-down mode t pd valid t cpded t is t ih t is t0 t1 t2 t3 t4 t5 ta0 ta1 nop dont care indicates a break in time scale t cke (min) t xp logic devices incorporated www.logicdevices.com 136 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 90 - p recharge p ower -d own (s low -e xit m ode ) e ntry and e xit notes: 1. any valid command not requiring a locked dll. 2. any valid command requiring a locked dll. ck ck# command pon pon pon cke t ck t ch t cl enter power-down mode exit power-down mode t pd valid 2 valid 1 pre t xpdll t cpded t is t ih t is t0 t1 t2 t3 t4 ta ta1 tb nop dont care indicates a break in time scale t xp t cke (min) f igure 91 - p ower -d own e ntry a fter read or read with a uto p recharge (rdap) t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 ta9 don t care transitioning data ta10 ta11 ta12 nop vali d read/ rdap nop nop nop nop nop nop nop nop nop ck ck # c ommand dq bl8 dq bc4 dqs, dqs# add ress ck e t cpded t is t pd power- down or self refresh entry indicates a break in time scale t rdpden di n + 3 di n + 1 di n + 2 di n rl = al + cl di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n+ 5 di n + 4 logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 92 - p ower -d own e ntry a fter write notes: 1. cke can go low 2 t ck earlier if bc4mrs. t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 tb 0 tb 1 tb 2 tb 3 tb 4 nop write valid nop nop nop nop nop nop nop nop nop nop nop ck ck # command dq bl8 dq bc4 dqs, dqs# add ress ck e t cpded power- down or self refresh entry 1 don t care transitioning data t wrpden di n + 3 di n + 1 di n + 2 di n t pd indicates a break in time scale di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n+ 4 t is wl = al + cwl t wr f igure 93 - p ower -d own e ntry a fter write with a uto p recharge (wrap) notes: 1. t wr is programmed through mr0[11:9] and represents t wr (min)ns/ t ck rounded up to the next integer t ck. 2. cke can go low 2 t ck earlier if bc4mrs. t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta 6 ta7 tb 0 tb 1 don t care transitioning data tb 2 tb 3 tb 4 nop wrap vali d nop nop nop ck ck# command dq bl8 dq bc4 dqs, dqs# add ress a10 cke t pd t wrapden power- down or self refresh entry 2 start internal pre char ge t cpded t is indicates a break in time scale di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 di n + 3 di n + 2 di n + 1 di n wr 1 wl = al + cwl nop nop nop nop nop nop nop nop logic devices incorporated www.logicdevices.com 138 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 94 - refresh to p ower -d own e ntry notes: 1. after cke goes high during t rfc, cke must remain high until t rfc is satisfied. ck ck# command refresh nop nop nop nop valid cke t ck t ch t cl t cpded t refpden t is t0 t1 t2 t3 ta0 ta1 ta2 tb0 t xp (min) t rfc (min) 1 dont care indicates a break in time scale t cke (min) t pd f igure 95 - activate to p ower -d own e ntry tcke ck ck# command address active nop nop cke t ck t ch t cl dont care t cpded t actpden valid t is t0 t1 t2 t3 t4 t5 t6 t7 t pd logic devices incorporated www.logicdevices.com 139 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 96 - precharge to p ower -d own e ntry ck ck# command address cke t ck t ch t cl dont care t cpded t prepden t is t0 t1 t2 t3 t4 t5 t6 t7 t pd all/single bank pre nop nop f igure 97 - mrs c ommand to p ower -d own e ntry ck ck# cke t ck t ch t cl t cpded address t is t0 t1 t2 ta0 ta1 ta2 ta3 ta4 t pd dont care indicates a break in time scale valid command mrs nop nop nop nop nop t mrspden logic devices incorporated www.logicdevices.com 140 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 98 - p ower -d own e xit to r efresh to p ower -d own e ntry notes: 1. t xp must be satisfied before issuing the command. 2. t xpdll must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. ck ck# cke t ck t ch t cl enter power-down mode enter power-down mode exit power-down mode t pd t cpded t is t ih t is t0 t1 t2 t3 t4 ta0 ta1 tb0 dont care indicates a break in time scale command nop nop nop nop refresh nop nop t xp 1 t xpdll 2 reset 7 k h 5 ( 6 ( 7 v l j q d o 5 ( 6 ( 7 ? l v d q d v \ q f k u r q r x v v l j q d o w k d w w u l j j h u v d q \ w l p h l w g u r s v / 2 : d q g w k h u h d u h q r u h v w u l f w l r q v d e r x w z k h q l w f d q j r / 2 : $ i w h u 5 ( 6 ( 7 ? l v g u l y h q / 2 : l w p x v w u h p d l q / 2 : i r u q v ' x u l q j w k l v w l p h w k h r x w s x w v d u h g l v d e o h g 2 ' 7 5 tt w x u q v r i i + , * + = d q g w k h ' ' 5 6 ' 5 $ 0 u h v h w v l w v h o i & . ( v k r x o g e h e u r x j k w / 2 : s u l r u w r 5 ( 6 ( 7 ? e h l q j g u l y h q + , * + $ i w h u 5 ( 6 ( 7 ? j r h v + , * + w k h 6 ' 5 $ 0 p x v w e h u h l q l w l d o l ] h g d v w k r x j k d q r u p d o s r z h u x s z h u h h [ h f x w h g v h h ) l j x u h $ o o u h i u h v k f r x q w h u v r q w k h 6 ' 5 $ 0 d u h 5 ( 6 ( 7 d q g g d w d v w r u h g l q w k h 6 ' 5 $ 0 l v d v v x p h g x q n q r z q d i w h u 5 ( 6 ( 7 ? k d v e h h q g u l y h q / 2 : logic devices incorporated www.logicdevices.com 141 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 99 - reset s equence cke r tt ba[2:0] all voltage supplies valid and stable high-z dm dqs high-z add ress a10 ck ck# t cl command nop t0 ta0 don t care t cl t is odt dq high-z tb 0 t dllk mr1 with dll enable mrs mrs ba0 = h ba1 = l ba2 = l ba0 = l ba1 = l ba2 = l code code code code vali d vali d vali d vali d normal operation mr2 mr3 mrs mrs ba0 = l ba1 = h ba2 = l ba0 = h ba1 = h ba2 = l code code code code tc0 td0 reset# sta ble an d vali d clo ck vali d vali d dram rea dy for external commands t1 t zq init a10 = h zq cl t is t ioz vali d vali d vali d system reset (warm boot) zq cal mr0 with dll reset t=10ns (min) t = 100ns (min) indicates a break in time scale t = 500s (min) t xpr t mrd t mrd t mrd t mod t (min) = max (10ns, 5 t ck) t ck logic devices incorporated www.logicdevices.com 142 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product on-die termination (odt) 2 ' 7 l v d i h d w x u h w k d w h q d e o h v w k h 6 ' 5 $ 0 w r h q d e o h g l v d e o h r q g l h w h u p l q d - w l r q u h v l v w d q f h i r u h d f k ' 4 / ' 4 6 [ / ' 4 6 [ ? 8 ' 4 6 [ 8 ' 4 6 [ ? / ' 0 [ d q g 8 ' 0 [ i r u w k h i r x u z r u g v f r q w d l q h g l q / ' , u v ' ' 5 l 0 2 ' 7 k h 2 ' 7 i h d w x u h l v g h v l j q h g w r l p s u r y h v l j q d o l q w h j u l w \ r i w k h p h p r u \ d u u d \ v x e v \ v w h p e \ h q d e o l q j w k h ' ' 5 p h p r u \ f r q w u r o o h u w r l q g h s h q - g h q w o \ w x u q r q r u r i i w k h 6 ' 5 $ 0 6 l q w h u q d o w h u p l q d w l r q u h v l v w d q f h i r u d q \ j u r x s l q j r i 6 ' 5 $ 0 g h y l f h v 7 k h 2 ' 7 i h d w x u h l v q r w v x s s r u w h g g x u l q j ' / / g l v d e o h p r g h $ v l p s o h i x q f w l r q d o u h s u h v h q w d w l r q r i w k h 6 ' 5 $ 0 2 ' 7 i h d - w x u h l v v k r z q l q ) l j x u h 7 k h v z l w f k l v h q d e o h g e \ w k h l q w h u q d o 2 ' 7 f r q - w u r o o r j l f z k l f k x v h v w k h h [ w h u q d o 2 ' 7 e d o o d q g r w k h u f r q w u r o l q i r u p d w l r q functional representation of odt 7 k h y d o x h r i 5 tt 2 ' 7 w h u p l q d w l r q y d o x h l v g h w h u p l q h g e \ w k h v h w w l q j v r i v h y h u d o p r g h u h j l v w h u e l w v v h h 7 d e o h 7 k h 2 ' 7 e d o o l v l j q r u h g z k l o h l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h p x v w e h w x u q h g r i i s u l r u w r 6 ( / ) 5 ( ) 5 ( 6 + h q w u \ r u l i p r g h u h j l v w h u v 0 5 d q g 0 5 d u h s u r j u d p p h g w r g l v d e o h 2 ' 7 2 ' 7 l v f r p s u l v h g r i q r p l q d o 2 ' 7 d q g g \ q d p l f 2 ' 7 p r g h v d q g h l w k h u r i w k h v h f d q i x q f w l r q l q v \ q f k u r q r x v r u d v \ q f k u r q r x v p r g h v z k h q w k h ' / / l v r i i g x u l q j 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 r u z k h q w k h ' / / l v v \ q f k u r q l ] - l q j 1 r p l q d o 2 ' 7 l v w k h e d v h w h u p l q d w l r q d q g l v x v h g l q d q \ d o o r z d e o h 2 ' 7 v w d w h ' \ q d p l f 2 ' 7 l v d s s o l h g r q o \ g x u l q j : 5 , 7 ( v d q g s u r y l g h v 2 7 ) v z l w f k l q j i u r p q r 5 tt or r tt _nom to r tt b : 5 7 k h d f w x d o h i i h f w l y h w h u p l q d w l r q 5 tt b ( ) ) p d \ e h g l i i h u h q w i u r p w k h 5 tt w d u j h w h g g x h w r q r q o l q h d u l w \ r i w k h w h u p l q d w l r q ) r u 5 tt b ( ) ) y d o x h v d q g f d o f x o d w l r q v v h h v 2 ' 7 & k d u d f w h u l v w l f v w odt v dd q/2 r tt switch dq, dqs, dqs#, to other circuitry such as rcv, . . . dm f igure 100 - o n -d ie t ermination nominal odt 2 ' 7 1 2 0 l v w k h e d v h w h u p l q d w l r q u h v l v w d q f h i r u h d f k d s s o l f d e o h e d o o h q d e o h g r u g l v d e o h g y l d 0 5 > @ v h h ) l j x u h d q g l w l v w x u q h g r q r u r i i y l d w k h 2 ' 7 e d o o t able 67: power-down m odes mr1[9,6,2] odt pin sdram termination state sdram state n o t e s r tt b 1 2 0 g l v d e o h g 2 ' 7 2 ) ) r tt b 1 2 0 g l v d e o h g 2 ' 7 2 1 r tt b 1 2 0 h q d e o h g 2 ' 7 2 ) ) r tt b 1 2 0 h q d e o h g 2 ' 7 2 1 r tt _nom reserved, odt on or off $ q \ y d o l g $ q \ y d o l g h [ f h s w 6 ( / ) 5 ( ) 5 ( 6 + 5 ( $ ' $ q \ y d o l g $ q \ y d o l g h [ f h s w 6 ( / ) 5 ( ) 5 ( 6 + 5 ( $ ' illegal 1,2 1,3 1,2 1,3 000 000 000-101 000-101 110 and 111 0 1 0 1 ; 3. 2 ' 7 p x v w e h g l v d e o h g g x u l q j 5 ( $ ' v 7 k h r tt b 1 2 0 y d o x h l v u h v w u l f w h g g x u l q j : 5 , 7 ( 6 ' \ q d p l f 2 ' 7 l v d s s o l f d e o h l i h q d e o h g 1 2 7 ( 6 1. $ v v x p h v g \ q d p l f 2 ' 7 l v g l v d e o h g 2. 2 ' 7 l v h q d e o h g d q g d f w l y h g x u l q j p r v w : 5 , 7 ( 6 i r u s u r s h u w h u p l q d w l r q e x w l w l v q r w l o o h j d o w r k d y h l w r i i g x u l q j : 5 , 7 ( 6 logic devices incorporated www.logicdevices.com 143 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 1 r p l q d o 2 ' 7 u h v l v w d q f h 5 tt b 1 2 0 l v g h i l q h g e \ 0 5 > @ d v v k r z q l q ) l j x u h 7 k h 5 tt b 1 2 0 w h u p l q d w l r q y d o x h d s s o l h v w r w k h r x w s x w s l q v s u h y l r x v o \ p h q w l r q h g ' ' 5 6 ' 5 $ 0 l 0 2 ' v v x s s r u w p x o w l s o h 5 tt b 1 2 0 y d o x h v e d v h g r q 5 = 4 q z k h u h q f d q e h r u d q g 5 = 4 l v : ? 5 tt b 1 2 0 w h u p l q d - w l r q l v d o o r z h g d q \ w l p h d i w h u w k h 6 ' 5 $ 0 l v l q l w l d o l ] h g f d o l e u d w h g d q g q r w s h u i r u p l q j 5 ( $ ' d f f h v v h v r u z k h q l w l v q r w l q 6 ( / ) 5 ( ) 5 ( 6 + p r g h : 5 , 7 ( d f f h v v x v h v 5 tt b 1 2 0 l g g \ q d p l f 2 ' 7 5 tt b : 5 l v g l v d e o h g , i 5 tt b 1 2 0 l v x v h g g x u l q j : 5 , 7 ( v r q o \ 5 = 4 5 = 4 d q g 5 = 4 d u h d o o r z h g v h h 7 d e o h 2 ' 7 w l p l q j v d u h v x p p d u l ] h g l q 7 d e o h d v z h o o d v o l v w h g l q 7 d e o h ( [ d p s o h v r i q r p l q d o 2 ' 7 w l p l q j d u h v k r z q l q f r q m x q f w l r q z l w k w k h v \ q f k u r q r x v p r g h r i r s h u d w l r q l q v 6 \ q f k u r q r x v 2 ' 7 0 r g h w t able 68: odt p arameter symbol description begins at defined to units 2 ' 7 u h j l v w h u h g + , * + 2 ' 7 u h j l v w h u h g + , * + 2 ' 7 u h j l v w h u h g + , * + 2 ' 7 u h j l v w h u h g + , * + 2 ' 7 u h j l v w h u h g + , * + r u : 5 , 7 ( u h j l v w u d w l r q z l w k 2 ' 7 + , * + : 5 , 7 ( u h j l v w u d w l r q z l w k 2 ' 7 + , * + & r p s o h w l r q r i 2 ' 7 / r q & r p s o h w l r q r i 2 ' 7 / r i i odtl on odtl off t $ 2 1 3 ' t $ 2 ) ) 3 ' 2 ' 7 + 2 ' 7 + t $ 2 1 t $ 2 ) 2 ' 7 v \ q f k u r q r x v w x u q r q g h o d \ 2 ' 7 v \ q f k u r q r x v w x u q r i i g h o d \ 2 ' 7 d v \ q f k u r q r x v r q g h o d \ 2 ' 7 d v \ q f k u r q r x v r q g h o d \ 2 ' 7 p l q l p x p + , * + w l p h d i w h u 2 ' 7 d v v h u w l r q r u : 5 , 7 ( % & 2 ' 7 p l q l p x p + , * + w l p h d i w h u : 5 , 7 ( % / 2 ' 7 w x u q r q u h o d w l y h w r 2 ' 7 / r q f r p s o h w l r q 2 ' 7 w x u q r i i u h o d w l y h w r 2 ' 7 / r i i f r p s o h w l r q r tt b 2 1 ? t $ 2 1 r tt b 2 1 ? t $ 2 ) r tt _on r tt _off 2 ' 7 u h j l v w h u h g / 2 : 2 ' 7 u h j l v w h u h g / 2 : r tt _on r tt _off & : / $ / & : / $ / 1-9 1-9 4 t & . 6 t & . 6 h h 7 d e o h 0.5 t & . ? t & . t & . t & . ns ns t & . t & . ps t & . definition for all ddr3 bins dynamic odt , q f h u w d l q d s s o l f d w l r q v w r i x u w k h u h q k d q f h v l j q d o l q w h j u l w \ r q w k h g d w d e x v l w l v g h v l u d e o h w k d w w k h w h u p l q d w l r q v w u h q j w k e h f k d q j h g z l w k r x w l v v x l q j d q 0 5 6 f r p p d q g h v v h q w l d o o \ f k d q j l q j w k h 2 ' 7 w h u p l q d w l r q u h v l v w d q f h r q w k h i o \ : l w k g \ q d p l f 2 ' 7 5 tt b : 5 h q d e o h g w k h 6 ' 5 $ 0 v z l w f k h v i u r p q r p l q d o 2 ' 7 5 tt b 1 2 0 w r g \ q d p l f 2 ' 7 z k h q e h j l q q l q j d : 5 , 7 ( e x u v w d q g v x e v h t x h q w o \ v z l w f k h v e d f n w r q r p l q d o 2 ' 7 d w w k h f r p s o h w l r q r i w k h : 5 , 7 ( e x u v w v h t x h q f h 7 k l v u h t x l u h p h q w d q g w k h v x s s r u w l q j ' < 1 $ 0 , & 2 ' 7 i h d w x u h r i w k h ' ' 5 6 ' 5 $ 0 p d n h v l w i h d v l e o h d q g l v g h v f u l e h g l q i x u w k h u g h w d l o e h o r z dynamic odt f unctional d escription : 7 k h g \ q d p l f 2 ' 7 p r g h l v h q d e o h g l i h l w k h u 0 5 > @ r u p 5 > @ l v v h w w r v w ' \ q d p l f 2 ' 7 l v q r w v x s s r u w h g g x u l q j ' / / g l v d e o h p r g h v r 5 tt b : 5 p x v w e h g l v d e o h g 7 k h g \ q d p l f 2 ' 7 i x q f w l r q l v g h v f u l e h g d v i r o o r z v x 7 z r 5 tt y d o x h v d u h d y d l o d e o h y 5 tt _nom and r tt b : 5 x 7 k h y d o x h r i 5 tt b 1 2 0 l v s u h v h o h f w h g y l d 0 5 > @ x 7 k h y d o x h i r u 5 tt b : 5 l v s u h v h o h f w h g y l d 0 5 > @ x ' x u l q j 6 ' 5 $ 0 r s h u d w l r q v z l w k r x w 5 ( $ ' r u : 5 , 7 ( f r p p d q g v w k h w h u p l q d w l r q l v f r q w u r o o h g d v i r o o r z v x 7 h u p l q d w l r q 2 1 2 ) ) w l p l q j l v f r q w u r o o h g y l d w k h 2 ' 7 e d o o d q g / $ 7 ( 1 & , ( 6 2 ' 7 o r q d q g 2 ' 7 / r i i x 1 r p l q d o w h u p l q d w l r q v w u h q j w k 5 tt _nom is used x : k h q d : 5 , 7 ( f r p p d q g : 5 : 5 $ 3 : 5 6 : 5 6 : 5 $ 3 6 : 5 $ 3 6 l v u h j l v w h u h g d q g l i g \ q d p l f 2 ' 7 l v h q d e o h g w k h 2 ' 7 w h u - p l q d w l r q l v f r q w u r o o h g d v i r o o r z v x $ o d w h q f \ r i 2 ' 7 / & 1 : d i w h u w k h : 5 , 7 ( f r p p d q g w h u p l q d w l r q v w u h q j w k 5 tt b 1 2 0 v z l w f k h v w r 5 tt b : 5 x $ / d w h q f \ r i 2 ' 7 / & : 1 i r u % / i l [ h g r u 2 7 ) r u 2 ' 7 / & : 1 i r u % & i l [ h g r u 2 7 ) d i w h u w k h : 5 , 7 ( f r p p d q g w h u p l q d w l r q strength r tt b : 5 v z l w f k h v e d f n w r 5 tt _nom x 2 1 2 ) ) w h u p l q d w l r q w l p l q j l v f r q w u r o o h g y l d w k h 2 ' 7 e d o o d q g g h w h u p l q h g e \ 2 ' 7 / r q 2 ' 7 / r i i 2 ' 7 + d q g 2 ' 7 + x during the t $ ' & w u d q v l w l r q z l q g r z w k h y d o x h r i 5 tt l v x q g h i l q h g 2 ' 7 l v f r q v w u d l q h g g x u l q j : 5 , 7 ( v d q g z k h q g \ q d p l f 2 ' 7 l v h q d e o h g v h h 7 d e o h nominal odt logic devices incorporated www.logicdevices.com 144 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 69: dynamic odt s pecific p arameters symbol description begins at defined t o units : 5 , 7 ( u h j l v w u d w l r q : 5 , 7 ( u h j l v w u d w l r q : 5 , 7 ( u h j l v w u d w l r q odtl & 1 : odtl & 1 : odtl & : 1 odtl & : 1 t $ ' & & k d q j h i u r p 5 tt _nom to r tt b : 5 & k d q j h i u r p 5 tt b : 5 w r 5 tt b 1 2 0 % & & k d q j h i u r p 5 tt b : 5 w r 5 tt b 1 2 0 % / r tt f k d q j h v n h z r tt v z l w f k h g i u r p 5 tt _nom to r tt b : 5 r tt v z l w f k h g i u r p 5 tt b : 5 w r 5 tt _nom r tt v z l w f k h g i u r p 5 tt b : 5 w r 5 tt _nom r tt w u d q v f r p s o h w h : / 4 t & . 2 ' 7 / 2 ) ) 6 t & . 2 ' 7 / 2 ) ) 0.5 t & . ? t & . t & . t & . t & . t & . definition for all ddr3 bins t able 70: mode registers for rtt_nom m9 m6 m2 rtt_nom (rzq) rtt_nom(ohms) rtt_nom mode restriction 0 0 0 0 1 1 1 1 2 i i 5 = 4 5 = 4 5 = 4 5 = 4 5 = 4 reserved reserved n/a 6 ( / ) 5 ( ) 5 ( 6 + 6 ( / ) 5 ( ) 5 ( 6 + : 5 , 7 ( n/a n/a 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 i i 60 120 40 20 30 reserved reserved mr1(rtt_nom) t able 71: mode registers for r tt _wr m10 m2 r tt _nom (rzq) r tt _nom(ohms) 0 0 1 1 n/a n/a n/a n/a 5 = 4 5 = 4 reserved n/a n/a n/a n/a 0 1 0 1 n/a n/a n/a n/a 60 120 reserved n/a n/a n/a n/a mr1(r tt _nom) dynamic odt off: write does not affect r tt _nom t able 72: timing diagrams for dynamic odt figure title figure 101 figure 102 figure 103 figure 104 figure 105 ' \ q d p l f 2 ' 7 2 ' 7 d v v h u w h g e h i r u h d q g d i w h u w k h : 5 , 7 ( % & ' \ q d p l f 2 ' 7 : l w k r x w : 5 , 7 ( f r p p d q g ' \ q d p l f 2 ' 7 2 ' 7 s l q d v v h u w h g w r j h w k h u z l w k : 5 , 7 ( f r p p d q g i r u & . f \ f o h v % / ' \ q d p l f 2 ' 7 2 ' 7 s l q d v v h u w h g z l w k : 5 , 7 ( f r p p d q g i r u & . f \ f o h v % & ' \ q d p l f 2 ' 7 2 ' 7 s l q d v v h u w h g z l w k : 5 , 7 ( f r p p d q g i r u & . f \ f o h v % & logic devices incorporated www.logicdevices.com 145 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 101 - d ynamic odt: odt a sserted b efore and a fter the write, bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom and r tt _ wr are enabled. 2. odth4 applies to first registering odt high and then to the registration of the write command. in this example, odth4 is satisfied if odt goes low at t8 (four clocks after the write command). t0 t1 t2 t3 t4 t5 t 6t7t8t9 odtl on odtl cw n 4 odtl cn w wl odtl off t10 t11 t12 t13 t14 t15 t17 t16 ck ck # command add ress r tt odt dq dqs, dqs# vali d wrs4 pon pon pon pon pon nop nop don t care transitioning r tt _ wr r tt _ nom r tt _ nom di n + 3 di n + 2 di n + 1 di n nop nop nop nop nop nop nop nop nop nop odth4 odth4 t aon (min) t adc (min) t adc (min) t aof (min) t aon (max) t adc (max) t adc (max) t aof (max) f igure 102 - d ynamic odt: w ithout write c ommand notes: 1. al = 0, cwl = 5. r tt _ nom is enabled and r tt _ wr is either enabled or disabled. 2. odth4 is defined from odt registered high to odt registered low; in this example, odth4 is satisfied. odt registered low at t5 is also legal. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtl off t10 t11 ck ck# r tt don t care transitionin g command vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d add ress dqs, dqs# dq odth4 odtl on t aon (max) t aon (min) t aof (min) t aof (max) odt r tt _ nom logic devices incorporated www.logicdevices.com 146 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 103 - d ynamic odt: odt p in a sserted t ogether with write c ommand for 6 c lock c ycles , bl8 notes: 1. via mrs or otf; al = 0, cwl = 5. if r tt _ nom can be either enabled or disabled, odt can be high. r tt _ wr is enabled. 2. in this example, odth8 = 6 is satisfied exactly. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtl cw n 8 odtl on odtl cn w wl t aof (max) t10 t11 ck ck# add ress r tt odt dq dqs, dqs# di b + 3 di b + 2 di b + 1 di b di b+ 7 di b + 6 di b + 5 di b + 4 vali d don t care transitioning command wrs8 nop nop nop nop nop nop nop nop nop nop nop r tt _ wr odth8 odtl off t adc (max) t aon (min) t aof (min) f igure 104 - d ynamic odt: odt p in a sserted with write c ommand for 6 c lock c ycles , bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom and r tt _ wr are enabled. 2. odth4 is defined from odt registered high to odt registered low, so in this example, odth4 is satisfied. odt registered low at t5 is also legal. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtl on odtl cn w wl t10 t11 ck ck# odtl cw n 4 dqs, dqs# address vali d don t care transitioning odtl off command wrs4 nop nop nop nop nop nop nop nop dq di n+ 3 di n + 2 di n + 1 di n t adc (min) t aof (min) t aof (max) t adc (max) t adc (max) t aon (min) odth4 odt r tt r tt _ wr r tt _ nom nop nop nop logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 105 - d ynamic odt: odt p in a sserted with write c ommand for 4 c lock c ycles , bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom can be either enabled or disabled. if disabled, odt can remain high. r tt _ wr is enabled. 2. in this example odth4 = 4 is satisfied exactly. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtl on odtl cn w wl t10 t11 ck ck# odtl cw n 4 dqs, dqs# add ress valid r tt _ wr command wrs4 nop nop nop nop nop nop nop nop nop don t care transitioning dq di n di n + 3 di n + 2 di n + 1 odth4 t adc (max) t aon (min) t aof (min) t aof (max) odtl off r tt r tt _ wr odt nop nop synchronous odt mode 6 \ q f k u r q r x v 2 ' 7 l v v h o h f w h g z k h q h y h u w k h ' / / l v w x u q h g r q d q g o r f n h g z k l o h 5 tt _nom or r tt b : 5 l v h q d e o h g % d v h g r q w k h 3 2 : ( 5 ' 2 : 1 g h i l q l w l r q w k h v h p r g h v d u h x $ q \ e d q n $ & 7 , 9 ( z l w k & . ( + , * + x 5 ( ) 5 ( 6 + p r g h z l w k & . ( + , * + x ' / ( p r g h z l w k & . ( + , * + x $ & 7 , 9 ( 3 2 : ( 5 ' 2 : 1 p r g h u h j d u g o h v v r i 0 5 > @ x 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h l i ' / / l v h q d e o h g g x u l q j 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 e \ mr0[12] odt latency and posted odt , q v \ q f k u r q r x v 2 ' 7 p r g h 5 tt w x u q v r q 2 ' 7 / r q f o r f n f \ f o h v d i w h u 2 ' 7 l v v d p s o h g + , * + e \ d u l v l q j f o r f n h g j h d q g w x u q v r i i 2 ' 7 / r i i f o r f n f \ f o h v d i w h u 2 ' 7 l v u h j l v w h u h g / 2 : e \ d u l v l q j f o r f n h g j h 7 k h d f w x d o r q r i i w l p h v y d u l h v e \ t $ 2 1 d q g t $ 2 ) d u r x q g h d f k f o r f n h g j h v h h 7 d e o h 7 k h 2 ' 7 / $ 7 ( 1 & < l v w l h g w r w k h : 5 , 7 ( / $ 7 ( 1 & < : / e \ 2 ' 7 / r q : / d q g 2 ' 7 / r i i : / 6 l q f h : 5 , 7 ( / $ 7 ( 1 & < l v p d g h x s r i & $ 6 : 5 , 7 ( / $ 7 ( 1 & < & : / d q g $ ' ' , 7 , 9 ( / $ 7 ( 1 & < $ / w k h $ / y d o x h s u r j u d p p h g l q w r w k h p r g h u h j l v- w h u 0 5 > @ d o v r d s s o l h v w r w k h 2 ' 7 v l j q d o 7 k h 6 ' 5 $ 0 u v l q w h u q d o 2 ' 7 v l j q d o l v g h o d \ h g d q x p e h u r i f o r f n f \ f o h v g h i l q h g e \ w k h $ / u h o d w l y h w r w k h h [ w h u q d o 2 ' 7 v l j q d o 7 k x v 2 ' 7 / r q & : / $ / y d q g 2 ' 7 / r i i & : / $ / y logic devices incorporated www.logicdevices.com 148 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product synchronous odt t iming p arameters 6 \ q f k u r q r x v 2 ' 7 p r g h x v h v w k h i r o o r z l q j w l p l q j s d u d p h w h u v 2 ' 7 / r q 2 ' 7 / r i i 2 ' 7 + 2 ' 7 + t $ 2 1 d q g t $ 2 ) v h h 7 d e o h d q g ) l j x u h 7 k h p l q l p x p 5 tt w x u q r q w l p h t $ 2 1 > 0 , 1 @ l v w k h s r l q w d w z k l f k w k h g h y l f h o h d y h v + , * + $ d q g 2 ' 7 u h v l v w d q f h e h j l q v w r w x u q r q 0 d [ l p x p 5 tt w x u q r q w l p h t $ 2 1 > 0 $ ; @ l v w k h s r l q w d w z k l f k 2 ' 7 u h v l v w d q f h l v i x o o \ r q % r w k d u h p h d v x u h g u h o d w l y h w r 2 ' 7 / r q 7 k h p l q l p x p 5 tt w x u q r i i w l p h t $ 2 ) > p l q @ l v w k h s r l q w d w z k l f k w k h g h y l f h v w d u w v w r w x u q r i i 2 ' 7 u h v l v w d q f h 0 d [ l p x p 5 tt w x u q r i i w l p h t $ 2 ) > 0 $ ; @ l v w k h s r l q w d w z k l f k 2 ' 7 k d v u h d f k h g + , * + = % r w k d u h p h d v x u h g i u r p 2 ' 7 / r i i : k h q 2 ' 7 l v d v v h u w h g l w p x v w u h p d l q + , * + x q w l o 2 ' 7 + l v v d w l v i l h g , i d : 5 , 7 ( f r p p d q g l v u h j l v w h u h g e \ w k h 6 ' 5 $ 0 z l w k 2 ' 7 + , * + w k h q 2 ' 7 p x v w u h p d l q + , * + x q w l o 2 ' 7 + % & r u 2 ' 7 + % / d i w h u w k h : 5 , 7 ( f r p p d q g v h h ) l j x u h 2 ' 7 + d q g 2 ' 7 + d u h p h d v x u h g i u r p 2 ' 7 u h j l v w h u h g + , * + w r 2 ' 7 u h j l v w h u h g / 2 : r u i u r p w k h u h j l v w u d w l r q r i d : 5 , 7 ( f r p p d q g x q w l o 2 ' 7 l v u h j l v w h u h g / 2 : t able 73: synchronous odt p arameters symbol description begins at defined to units 2 ' 7 u h j l v w h u h g + , * + 2 ' 7 u h j l v w h u h g + , * + 2 ' 7 u h j l v w h u h g + , * + r u : 5 , 7 ( u h j l v w u d w l r q z l w k 2 ' 7 + , * + : 5 , 7 ( u h j l v w u d w l r q z l w k 2 ' 7 + , * + & r p s o h w l r q r i 2 ' 7 / r q & r p s o h w l r q r i 2 ' 7 / r i i odtl on odtl off 2 ' 7 + 2 ' 7 + t $ 2 1 t $ 2 ) 2 ' 7 v \ q f k u r q r x v 7 8 5 1 2 1 g h o d \ 2 ' 7 v \ q f k u r q r x v 7 8 5 1 2 ) ) g h o d \ 2 ' 7 0 l q l p x p + , * + w l p h d i w h u 2 ' 7 d v v h u w l r q r u : 5 , 7 ( % & 2 ' 7 0 l q l p x p + , * + w l p h d i w h u : 5 , 7 ( % / 2 ' 7 7 8 5 1 2 1 u h o d w l y h w r 2 ' 7 / r q f r p s o h w l r q 2 ' 7 7 8 5 1 2 ) ) u h o d w l y h w r 2 ' 7 / r i i f r p s o h w l r q r tt b 2 1 ? t $ 2 1 r tt b 2 ) ) ? t $ 2 ) 2 ' 7 u h j l v w h u h g / 2 : 2 ' 7 u h j l v w h u h g / 2 : r tt _on r tt _off & : / $ / & : / $ / 4 t f . 6 t f . 6 h h 7 d e o h 0.5 t f . ? t f . t & . t & . t & . t & . ps t & . definition for all ddr3 bins f igure 106 - s ynchronous odt notes: 1. al = 3; cwl = 5; odtl on = wl = 6.0; odtl off = wl - 2 = 6. r tt _ nom is enabled. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 cw l - al = 3 al = 3 t aon (max) t10 t11 t12 ck ck # r tt odt r tt _ nom ck e odtl off = cwl + al - 2 odtl on = cwl + al - 2 odth4 (min) t aon (min) logic devices incorporated www.logicdevices.com 149 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 107 - s ynchronous odt (bc4) notes: 1. wl = 7. r tt _ nom is enabled. r tt _ wr is disabled. 2. odt must be held high for at least odth4 after assertion (t1). 3. odt must be kept high odth4 (bc4) or odth8 (bl8) after the write command (t7). 4. odth is measured from odt first registered high to odt first registered low or from the registration of the write command with odt high to odt registered low. 5. although odth4 is satisfied from odt registered high at t6, odt must not go low before t11 as odth4 must also be satisfied from the registration of the write command at t7. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aof (max) t aof (min) t aon (max) t aof (max) t10 t11 t12 t13 t14 t15 t17 t16 ck ck# r tt ck e nop wrs4 nop nop nop nop nop nop command don t care transitioning t aon (min) r tt _ nom odtloff = wl - 2 odth4 (min) odth4 odtl off = wl - 2 odtl on = wl - 2 t aon (min) t aon (max) odth4 odtl on = wl - 2 t aof (min) odt r tt _ nom nop nop nop nop nop nop nop nop nop nop odt off d uring reads $ v w k h ' ' 5 6 ' 5 $ 0 f d q q r w w h u p l q d w h d q g g u l y h d w w k h v d p h w l p h 5 tt p x v w e h g l v d e o h g d w o h d v w r q h k d o i f o r f n f \ f o h e h i r u h w k h 5 ( $ ' s u h d p e o h e \ g u l y l q j w k h 2 ' 7 e d o o / 2 : 5 tt p d \ q r w e h h q d e o h g x q w l o w k h h q g r i w k h s r v w d p e o h d v v k r z q l q ) l j x u h f igure 108 - odt d uring read s notes: 1. odt must be disabled externally during reads by driving odt low. for example, cl = 6; al = cl - 1 = 5; rl = al + cl = 11; cwl = 5; odtl on = cwl + al - 2 = 8; odtl off = cwl + al - 2 = 8. r tt _ nom is enabled. r tt _ wr is a dont care. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t17 t16 ck ck# vali d add ress di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b+ 5 di b+ 4 dq dqs, dqs# don t care transitioning command nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop read odtl on = cwl + al - 2 odt t aon (max) rl = al + cl odtl off = cwl + al - 2 t aof (min) r tt r tt _ nom r tt _ nom t aof (max) logic devices incorporated www.logicdevices.com 150 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product asynchronous odt mode $ v \ q f k u r q r x v 2 ' 7 p r g h l v d y d l o d e o h z k h q w k h 6 ' 5 $ 0 u x q v l q ' / / 2 1 p r g h d q g z k h q h l w k h u 5 tt _nom or r tt b : 5 l v h q d e o h g k r z h y h u w k h ' / / l v w h p - s r u d u l o \ w x u q h g r i i l q 3 5 ( & + $ 5 * ( ' 3 2 : ( 5 ' 2 : 1 v w d q g e \ y l d 0 5 > @ $ g g l w l r q d o o \ 2 ' 7 r s h u d w h v d v \ q f k u r q r x v o \ z k h q w k h ' / / l v v \ q f k u r q l ] l q j d i w h u e h l q j 5 ( 6 ( 7 6 h h v 3 2 : ( 5 ' 2 : 1 0 2 ' ( w i r u g h i l q l w l r q d q g j x l g d q f h r y h u 3 2 : ( 5 ' 2 : 1 g h w d l o v , q d v \ q f k u r q r x v 2 ' 7 w l p l q j p r g h w k h l q w h u q d o 2 ' 7 f r p p d q g l v q r w g h o d \ h g e \ $ / u h o d w l y h w r w k h h [ w h u q d o 2 ' 7 f r p p d q g , q d v \ q f k u r q r x v 2 ' 7 p r g h 2 ' 7 f r q w u r o v 5 tt e \ d q d o r j w l p h 7 k h w l p l q j s d u d p h w h u v t $ 2 1 3 ' d q g t $ 2 ) 3 ' v h h 7 d e o h u h s o d f h 2 ' 7 / r q t $ 2 1 d q g 2 ' 7 / r i i t $ 2 ) u h v s h f w l y h o \ z k h q 2 ' 7 r s h u d w h v d v \ q f k u r q r x v o \ v h h ) l j x u h 7 k h p l q l p x p 5 tt w x u q r q w l p h t $ 2 1 3 ' > 0 , 1 @ l v w k h s r l q w d w z k l f k w k h g h y l f h w h u p l q d w l r q f l u f x l w o h d y h v + , * + = d q g 2 ' 7 u h v l v w d q f h e h j l q v w r w x u q r q 0 d [ l - p x p 5 tt w x u q r q w l p h t $ 2 1 3 ' > 0 $ ; @ l v w k h s r l q w d w z k l f k 2 ' 7 u h v l v w d q f h l v i x o o \ r q t $ 2 1 3 ' 0 , 1 d q g t $ 2 1 3 ' 0 $ ; d u h p h d v x u h g i u r p 2 ' 7 e h l q j v d p s o h g + , * + 7 k h p l q l p x p 5 tt w x u q r i i w l p h t $ 2 ) 3 ' > 0 , 1 @ l v w k h s r l q w d w z k l f k w k h g h y l f h w h u p l q d w l r q f l u f x l w v w d u w v w r w x u q r i i 2 ' 7 u h v l v w d q f h 0 d [ l p x p 5 tt w x u q r i i w l p h t $ 2 ) 3 ' > 0 $ ; @ l v w k h s r l q w d w z k l f k 2 ' 7 k d v u h d f k h g + , * + = t $ 2 ) 3 ' 0 , 1 d q g t $ 2 ) 3 ' 0 $ ; d u h p h d v x u h g i u r p 2 ' 7 e h l q j v d p s o h g / 2 : t able 74: asynchronous odt t iming p arameters for a ll s peed b ins symbol description min max units t $ 2 1 pd t $ 2 ) pd $ v \ q f k u r q r x v 5 tt 7 8 5 1 2 1 g h o d \ 3 2 : ( 5 ' 2 : 1 z l w k ' / / r i i $ v \ q f k u r q r x v 5 tt 7 8 5 1 2 ) ) g h o d \ 3 2 : ( 5 ' 2 : 1 z l w k ' / / r i i 2 2 8.5 8.5 ns ns f igure 109 - a synchronous odt t iming with f ast odt t ransition notes: 1. al is ignored. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aonpd (max) t aofpd (max) t10 t11 t12 t13 t14 t15 t17 t16 ck ck # r tt odt r tt _ nom don t care transitioning ck e t ih t is t ih t is t aofpd (min) t aonpd (min) logic devices incorporated www.logicdevices.com 151 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product t able 75: odt p arameters for power-down (dll off) e ntry and e xit t ransition p eriod description min max 3 2 : ( 5 ' 2 : 1 h q w u \ w u d q v l w l r q s h u l r g 3 2 : ( 5 ' 2 : 1 h q w u \ 3 2 : ( 5 ' 2 : 1 h q w u \ w u d q v l w l r q 3 2 : ( 5 ' 2 : 1 h [ l w odt to r tt 7 8 5 1 2 1 g h o d \ 2 ' 7 / r q : / odt to r tt 7 8 5 1 2 ) ) g h o d \ 2 ' 7 / r i i : / t $ 1 pd * u h d w h u r i t $ 1 pd or t 5 ) & 5 ( ) 5 ( 6 + w r & . ( / 2 : t $ 1 3 ' t ; 3 ' / / : / * u h d w h u r i 2 ' 7 / r i i r u 2 ' 7 / r q / h v v h u r i t $ 1 pd 0 , 1 > q v @ r u odl on x t & . t $ 2 1 0 , 1 / h v v h u r i t $ 2 ) pd 0 , 1 > q v @ r u 2 ' / r i i [ t & . t $ 2 ) 0 , 1 / h v v h u r i t $ 1 pd 0 , 1 > q v @ r u odl on x t & . t $ 2 1 0 , 1 / h v v h u r i t $ 2 ) pd 0 , 1 > q v @ r u 2 ' / r i i [ t & . t $ 2 ) 0 , 1 synchronous to asynchronous odt mode transition (power-down entry) 7 k h u h l v d w u d q v l w l r q s h u l r g d u r x q g 3 2 : ( 5 ' 2 : 1 ( 1 7 5 < 3 ' ( z k h u h w k h 6 ' 5 $ 0 u v 2 ' 7 p d \ h [ k l e l w h l w k h u v \ q f k u r q r x v r u d v \ q f k u r q r x v e h k d y l r u 7 k l v w u d q v l w l r q s h u l r g r f f x u v l i w k h ' / / l v v h o h f w h g w r e h r i i z k h q l q 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h e \ w k h v h w w l q j r i 0 5 > @ 3 2 : ( 5 ' 2 : 1 h q w u \ e h j l q v t $ 1 3 ' s u l r u w r & . ( i l u v w e h l q j u h j l v w h u h g / 2 : d q g l w h q g v z k h q & / ( l v i l u v w u h j l v w h u h g / 2 : t $ 1 3 ' l v h t x d o w r w k h j u h d w h u r i 2 ' 7 / r i i t & . r u 2 ' 7 / r q t & . , i d 5 ( ) 5 ( 6 + f r p p d q g k d v e h h q l v v x h g d q g l w l v l q s u r j u h v v z k h q & . ( j r h v / 2 : 3 2 : ( 5 ' 2 : 1 h q w u \ z l o o h q g t 5 ) & d i w h u w k h 5 ( ) 5 ( 6 + f r p p d q g u d w k h u w k d q z k h q & . ( l v i l u v w u h j l v w h u h g / 2 : 3 2 : ( 5 ' 2 : 1 ( 1 7 5 < z l o o w k h q e h f r p h w k h j u h d w h u r i t $ 1 3 ' d q g t 5 ) & y 5 ( ) 5 ( 6 + f r p p d q g w r & . ( u h j l v w h u h g / 2 : 2 ' 7 d v v h u w l r q g x u l q j 3 2 : ( 5 ' 2 : 1 ( 1 7 5 < u h v x o w v l q d q 5 tt f k d q j h d v h d u o \ d v w k h o h v v h u r i t $ 2 1 3 ' 0 , 1 d q g 2 ' 7 / r q [ t & . t $ 2 1 0 , 1 r u d v o d w h d v w k h j u h d w h u r i t $ 2 1 3 ' 0 $ ; d q g 2 ' 7 / r q [ t & . t $ 2 1 0 $ ; 2 ' 7 g h d v v h u w l r q g x u l q j 3 2 : ( 5 ' 2 : 1 ( 1 7 5 < p d \ u h v x o w l q d q 5 tt f k d q j h d v h d u o \ d v w k h o h v v h u r i t $ 2 ) 3 ' 0 , 1 d q g 2 ' 7 / r i i [ t & . t $ 2 ) 0 , 1 r u d v o d w h d v w k h j u h d w h u r i t $ 2 ) 3 ' 0 $ ; d q g 2 ' 7 / r i i [ t & . t $ 2 ) 0 $ ; 7 d e o h v x p p d u l ] h v w k h v h s d u d p h w h u v , i w k h $ / k d v d o d u j h y d o x h w k h x q f h u w d l q w \ r i w k h v w d w h r i 5 tt e h f r p h v t x l w h o d u j h 7 k l v l v e h f d x v h 2 ' 7 / r q d q g 2 ' 7 / r i i d u h g h u l y h g i u r p w k h : / d q g : / l v h t x d o w r & : / $ / ) l j x u h v k r z v w k u h h g l i i h u h q w f d v h v x 2 ' 7 b $ 6 \ q f k u r q r x v e h k d y l r u e h i r u h t $ 1 3 ' x 2 ' 7 b % 2 ' 7 v w d w h f k d q j h v g x u l q j w k h w u d q v l w l r q s h u l r g z l w k t $ 2 1 3 ' 0 , 1 o h v v w k d q 2 ' 7 / r q [ t & . t $ 2 1 0 , 1 d q g t $ 2 1 3 ' 0 $ ; greater than odtl on x t & . t $ 2 1 0 $ ; x 2 ' 7 b & 2 ' 7 v w d w h f k d q j h v d i w h u w k h w u d q v l w l r q s h u l r g z l w k d v \ q f k u r q r x v e h k d y l r u logic devices incorporated www.logicdevices.com 152 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product asynchronous to synchronous odt mode transition (power-down exit) 7 k h 6 ' 5 $ 0 u v 2 ' 7 p d \ h [ k l e l w h l w k h u d v \ q f k u r q r x v r u v \ q f k u r q r x v e h k d y l r u g x u l q j 3 2 : ( 5 ' 2 : 1 ( ; , 7 3 ' ; 7 k l v w u d q v l w l r q s h u l r g r f f x u v l i w k h ' / / l v v h o h f w h g w r e h r i i z k h q l q 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h e \ v h w w l q j 0 5 > @ w r v w 3 2 : ( 5 ' 2 : 1 h [ l w e h j l q v t $ 1 3 ' s u l r u w r & . ( i l u v w e h l q j u h j l v - w h u h g + , * + d q g l w h q g v t ; 3 ' / / d i w h u & . ( l v i l u v w u h j l v w h u h g + , * + t $ 1 3 ' l v h t x d o w r w k h j u h d w h u r i 2 ' 7 / r i i t & . r u 2 ' 7 / r q t & . 7 k h w u d q v l w l r q s h u l r g is t $ 1 3 ' s o x v t ; 3 ' / / 2 ' 7 d v v h u w l r q g x u l q j 3 2 : ( 5 ' 2 : 1 h [ l w u h v x o w v l q d q 5 tt f k d q j h d v h d u o \ d v w k h o h v v h u r i t $ 2 1 3 ' 0 , 1 d q g 2 ' 7 / r q [ t & . t $ 2 1 0 , 1 r u d v o d w h d v w k h j u h d w h u r i t $ 2 1 3 ' 0 $ ; d q g 2 ' 7 / r q [ t & . t $ 2 1 0 $ ; 2 ' 7 g h d v v h u w l r q g x u l q j 3 2 : ( 5 ' 2 : 1 ( ; , 7 p d \ u h v x o w l q d q 5 tt f k d q j h d v h d u o \ d v w k h o h v v h u r i t $ 2 ) 3 ' 0 , 1 d q g 2 ) 7 / r i i [ t & . t $ 2 ) 0 , 1 r u d v o d w h d v w k h j u h d w h u r i t $ 2 ) 3 ' 0 $ ; d q g 2 ' 7 / r i i [ t & . t $ 2 ) 0 $ ; 7 d e o h v x p p d u l ] h v w k h v h s d u d p h w h u v , i w k h $ / k d v d o d u j h y d o x h w k h x q f h u w d l q w \ r i w k h 5 tt v w d w h e h f r p h v t x l w h o d u j h 7 k l v l v e h f d x v h 2 ' 7 / r q d q g 2 ' 7 / r i i d u h g h u l y h g i u r p w k h : / d q g w k h : / l v h t x d o w r & : / $ / ) l j x u h v k r z v w k u h h g l i i h u h q w f d v h v x 2 ' 7 & $ v \ q f k u r q r x v e h k d y l r u e h i r u h t $ 1 3 ' x 2 ' 7 % 2 ' 7 v w d w h f k d q j h v g x u l q j w k h w u d q v l w l r q s h u l r g z l w k t $ 2 ) 3 ' 0 , 1 o h v v w k d q 2 ' 7 / r i i [ t & . t $ 2 ) 0 , 1 d q g 2 ' 7 / r i i [ t & . t $ 2 ) 0 $ ; j u h d w h u w k d q t $ 2 ) 3 ' 0 $ ; x 2 ' 7 $ 2 ' 7 v w d w h f k d q j h v d i w h u w k h w u d q v l w l r q s h u l r g z l w k v \ q f k u r q r x v u h v s r q v h f igure 110 - s ynchronous to a synchronous t ransition d uring p recharge p ower -d own (dll o ff ) e ntry notes: 1. al = 0; cwl = 5; odtl off = wl - 2 = 3. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aofpd (max) odtl off t10 t11 t12 t13 ta0 ta1 ta3 ta2 ck ck# dram r tt b asynchronous or synchronous r tt _ nom dram r tt c asynchronous r tt _ nom don t care transitioning ck e nop nop nop nop nop command nop ref nop nop nop nop nop nop nop nop nop nop nop pde transition perio d indicates a break in time scale odtl off + t aofpd (min) t aofpd (max) t aofpd (min) odtl off + t aofpd (max) t aofpd (min) t anpd t aof (min) t aof (max) dram r tt a synchronous r tt _ nom odt a synchronous odt c asynchronous odt b asynchronous or synchronous t rfc (min) logic devices incorporated www.logicdevices.com 153 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product f igure 111 - a synchronous to s ynchronous t ransition d uring p recharge p ower -d own (dll o ff ) e xit notes: 1. cl = 6; al = cl - 1; cwl = 5; odtl off = wl - 2 = 8. t0 t1 t2 ta0 ta1 ta2 ta3 ta4 ta5 ta 6 t b0 tb1 tb2 tc0 tc1 td 0 td 1 tc2 ck ck# don t care transitioning odt c synchronous pon pon nop command nop nop nop nop r tt b asynchronous or synchronous dram r tt a asynchronous dram r tt c synchronous r tt _ nom nop nop odt b asynchronous or synchronous ck e t aof (min) r tt _ nom indicates a break in time scale odtl off + t aof (min) t aofpd (max) odtl off + t aof (max) t xpdll t aof (max) odtl off odt a asynchronous pdx transition period t aofpd (min) t aofpd (max) t anpd t aofpd (min) r tt _ nom nop nop nop nop nop logic devices incorporated www.logicdevices.com 154 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product asynchronous to synchronous odt mode transition (short cke pulse) , i w k h w l p h l q w k h 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 r u , ' / ( v w d w h v l v y h u \ v k r u w v k r u w & . ( / 2 : s x o h v w k h 3 2 : ( 5 ' 2 : 1 ( 1 7 5 < d q g 3 2 : ( 5 ' 2 : 1 ( ; , 7 w u d q v l w l r q s h u l r g v z l o o r y h u o d s : k h q r y h u o d s r f f x u v w k h u h v s r q v h r i w k h 6 ' 5 $ 0 u v 5 tt w r d f k d q j h l q w k h 2 ' 7 v w d w h p d \ e h v \ q f k u r q r x v r u d v \ q f k u r q r x v i u r p w k h v w d u w r i w k h 3 2 : ( 5 ' 2 : 1 ( 1 7 5 < w u d q v l w l r q s h u l r g w r w k h h q g r i w k h 3 2 : ( 5 ' 2 : 1 ( ; , 7 w u d q v l w l r q s h u l r g h y h q l i w k h ( 1 7 5 < s h u l r g h q g v o d w h u w k d q w k h ( ; , 7 s h u l r g v h h ) l j x u h , i w k h w l p h l q w k h l g o h v w d w h l v y h u \ v k r u w v k r u w & . ( + , * + s x o v h w k h 3 2 : ( 5 ' 2 : 1 ( ; , 7 d q g 3 2 : ( 5 ' 2 : 1 ( 1 7 5 < w u d q v l w l r q s h u l r g v r y h u o d s : k h q w k l v r y h u o d s r f f x u v w k h u h v s r q v h r i w k h 6 ' 5 $ 0 u v 5 tt w r d f k d q j h l q w k h 2 ' 7 v w d w h p d \ e h v \ q f k u r q r x v r u d v \ q f k u r q r x v i u r p w k h v w d u w r i w k h 3 2 : ( 5 ' 2 : 1 ( ; , 7 w u d q v l w l r q s h u l r g w r w k h h q g r i w k h 3 2 : ( 5 ' 2 : 1 ( 1 7 5 < w u d q v l w l r q s h u l r g v h h ) l j x u h f igure 112 - t ransition p eriod for s hort cke low c ycles with e ntry and e xit p eriod o verlapping notes: 1. al = 0, wl = 5, t anpd = 4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ta0 ta1 ta2 ta3 ta4 ck ck# ck e command don t care transitionin g t xpdll t rfc (min) nop nop nop nop nop nop nop nop nop nop ref pon pon nop nop pde transition period pdx transition perio d indicates a break in time scale t anpd short cke low transition period (r tt chan ge asynchronous or syn chronous) t anpd f igure 113 - t ransition p eriod for s hort cke high c ycles with e ntry and e xit p eriod o verlapping notes: 1. al = 0, wl = 5, t anpd = 4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ck ck# c ommand don t care transitionin g nop nop nop nop nop nop nop nop nop nop nop pon pon nop nop nop t anpd t xpdll indicates a break in time scale t a 0 t a 1 t a 2 t a 3 t a 4 cke short cke high transition period (r tt chan ge asynchronous or synchonous) t anpd logic devices incorporated www.logicdevices.com 155 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product list of figures ) l j x u h ' ' 5 3 d u w 1 x p e h u v ) l j x u h 6 l p s o l i l h g 6 w d w h ' l d j u d p ) l j x u h ) x q f w l r q d o % o r f n ' l d j u d p ) l j x u h 6 ' 5 $ 0 ' ' 5 3 l q r x w 7 r s 9 l h z ) l j x u h 0 h f k d q l f d o ' u d z l q j ) l j x u h , q s x w 6 l j q d o ) l j x u h 2 y h u v k r r w 6 s h f l i l f d w l r q v ) l j x u h 8 q g h u v k r r w 6 s h f l i l f d w l r q v ) l j x u h 9 , ; i r u ' l i i h u h q w l d o 6 l j q d o v ) l j x u h 6 l q j o h ( q g h g 5 h t x l u h p h q w v i r u ' l i i h u h q w l d o 6 l j q d o v ) l j x u h ' h i l q l w l r q r i ' l i i h u h q w l d o $ & 6 z l q j d q g t ' 9 $ & ) l j x u h 1 r p l q d o 6 o h z 5 d w h ' h i l q l w l r q i r u 6 l q j o h ( q g h g , q s x w 6 l j q d o v ) l j x u h 1 r p l q d o ' l i i h u h q w l d o , q s x w 6 o h z 5 d w h ' h i l q l w l r q i r u ' 4 6 ' 4 6 d q g & . & . ) l j x u h 2 ' 7 / h y h o v d q g , 9 & k d u d f w h u l v w l f v ) l j x u h 2 ' 7 7 l p l q j 5 h i h u h q f h / r d g figure 16: t $ 2 1 d q g t $ 2 ) ' h i l q l w l r q v ) l j x u h t $ 2 1 3 ' d q g t $ 2 ) 3 ' ' h i l q l w l r q figure 18: t $ ' & ' h i l q l w l r q figure 19: output driver 40 figure 20: dq output signal 45 ) l j x u h ' l i i h u h q w l d o 2 x w s x w 6 l j q d o ) l j x u h 5 h i h u h q f h 2 x w s x w / r d g i r u $ & 7 l p l q j d q g 2 x w s x w 6 o h z 5 d w h ) l j x u h 1 r p l q d o 6 o h z 5 d w h ' h i l q l w l r q i r u 6 l q j o h ( q g h g 2 x w s x w 6 l j q d o v ) l j x u h 1 r p l q d o ' l i i h u h q w l d o 2 x w s x w 6 o h z 5 d w h ' h i l q l w l r q i r u ' 4 6 ' 4 6 ) l j x u h 1 r p l q d o 6 o h z 5 d w h d q g t 9 $ & i r u t , 6 & r p p d q g d q g $ g g u h v v & o r f n ) l j x u h 1 r p l q d o 6 o h z 5 d w h i r u t , + & r p p d q g d q g $ g g u h v v & o r f n ) l j x u h 7 d q j h q w / l q h i r u t , 6 & r p p d q g d q g $ g g u h v v & o r f n ) l j x u h 7 d q j h q w / l q h i r u t , + & r p p d q g d q g $ g g u h v v & o r f n ) l j x u h 1 r p l q d o 6 o h z 5 d w h d q g t 9 $ & i r u t ' 6 ' 4 6 w u r e h ) l j x u h 1 r p l q d o 6 o h z 5 d w h i r u t ' + ' 4 6 w u r e h ) l j x u h 1 r p l q d o 6 o h z 5 d w h d q g t 9 $ & i r u t ' 6 ' 4 6 w u r e h ) l j x u h 1 r p l q d o 6 o h z 5 d w h i r u t ' + ' 4 6 w u r e h ) l j x u h 5 h i u h v k 0 r g h ) l j x u h ' / / ( q d e o h 0 r g h w r ' / / ' l v d e o h 0 r g h ) l j x u h ' / / ' l v d e o h 0 r g h w r ' / / ( q d e o h 0 r g h ) l j x u h ' / / ' l v d e o h t ' 4 6 & . 7 l p l q j ) l j x u h & k d q j h ) u h t x h q f \ ' x u l q j 3 u h f k d u j h 3 r z h u ' r z q ) l j x u h : u l w h / h y h o l q j & r q f h s w ) l j x u h : u l w h / h y h o l q j 6 h t x h q f h ) l j x u h ( [ l w : u l w h / h y h o l q j ) l j x u h , q l w l d o l ] d w l r q 6 h t x h q f h ) l j x u h 0 5 6 w r 0 5 6 & r p p d q g 7 l p l q j t 0 5 ' ) l j x u h 0 5 6 w r q r q 0 5 6 & r p p d q g 7 l p l q j t 0 2 ' ) l j x u h 0 r g h 5 h j l v w h u 0 5 ' h i l q l w l r q v ) l j x u h 5 ( $ ' / d w h q f \ ) l j x u h 0 r g h 5 h j l v w h u 0 5 ' h i l q l w l r q ) l j x u h 5 ( $ ' / d w h q f \ $ / & / ) l j x u h 0 r g h 5 h j l v w h u 0 5 ' h i l q l w l r q logic devices incorporated www.logicdevices.com 156 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product ) l j x u h & $ 6 : u l w h / d w h q f \ ) l j x u h 0 r g h 5 h j l v w h u 0 5 ' h i l q l w l r q ) l j x u h 0 x o w l s x u s r v h 5 h j l v w h u 0 3 5 % o r f n ' l d j u d p ) l j x u h 0 3 5 6 \ v w h p 5 h d g & d o l e u d w l r q z l w k % / ) l [ h g % x u v w 2 u g h u 6 l q j o h 5 h d g r x w ) l j x u h 0 3 5 6 \ v w h p 5 h d g & d o l e u d w l r q z l w k % / ) l [ h g % x u v w 2 u g h u % d f n w r % d f n 5 h d g r x w ) l j x u h 0 3 5 6 \ v w h p 5 h d g & d o l e u d w l r q z l w k % & / r z h u 1 l e e o h w k h q 8 s s h u 1 l e e o h ) l j x u h 0 3 5 6 \ v w h p 5 h d g & d o l e u d w l r q z l w k % & 8 s s h u 1 l e e o h w k h q / r z h u 1 l e e o h ) l j x u h = 4 & d o l e u d w l r q 7 l p l q j = 4 & / d q g = 4 & 6 ) l j x u h ( [ d p s o h 0 h h w l q j t 5 5 ' 0 , 1 d q g t 5 & ' 0 , 1 ) l j x u h ( [ d p s o h t ) $ : ) l j x u h 5 ( $ ' / d w h q f \ ) l j x u h & r q v h f x w l y h 5 ( $ ' % x u v w v % / ) l j x u h & r q v h f x w l y h 5 ( $ ' % x u v w v % & ) l j x u h 1 r q f r q v h f x w l y h 5 ( $ ' % x u v w v ) l j x u h 5 ( $ ' % / w r : 5 , 7 ( % / ) l j x u h 5 ( $ ' % & w r : 5 , 7 ( % & 2 7 ) ) l j x u h 5 ( $ ' w r 3 5 ( & + $ 5 * ( % / ) l j x u h 5 ( $ ' w r 3 5 ( & + $ 5 * ( % & ) l j x u h 5 ( $ ' w r 3 5 ( & + $ 5 * ( $ / & / ) l j x u h 5 ( $ ' z l w k $ x w r 3 u h f k d u j h $ / & / ) l j x u h ' d w d 2 x w s x w 7 l p l q j t ' 4 6 4 d q g ' d w d 9 d o l g : l q g r z ) l j x u h ' d w d 6 w u r e h 7 l p l q j 5 ( $ ' v ) l j x u h 0 h w k r g i r u & d o f x o d w l q j t / = d q g t + = ) l j x u h t 5 3 5 ( 7 l p l q j ) l j x u h t 5 3 6 7 7 l p l q j ) l j x u h t : 3 5 ( 7 l p l q j ) l j x u h t : 3 6 7 7 l p l q j ) l j x u h : u l w h % x u v w ) l j x u h & r q v h f x w l y h : 5 , 7 ( % / w r : 5 , 7 ( % / ) l j x u h & r q v h f x w l y h : 5 , 7 ( % & y l d 0 5 6 r u 2 7 ) ) l j x u h 1 r q f r q v h f x w l y h : 5 , 7 ( w r : 5 , 7 ( ) l j x u h : 5 , 7 ( % / w r 5 ( $ ' % / ) l j x u h : 5 , 7 ( w r 5 ( $ ' % & 0 r g h 5 h j l v w h u 6 h w w l q j ) l j x u h : 5 , 7 ( % & 2 7 ) w r 5 ( $ ' % & 2 7 ) ) l j x u h : 5 , 7 ( % / w r 3 5 ( & + $ 5 * ( ) l j x u h : 5 , 7 ( % & 0 r g h 5 h j l v w h u 6 h w w l q j w r 3 5 ( & + $ 5 * ( ) l j x u h : 5 , 7 ( % & 2 7 ) w r 3 5 ( & + $ 5 * ( ) l j x u h ' d w d , q s x w 7 l p l q j ) l j x u h 6 h o i 5 h i u h v k ( q w u \ ( [ l w 7 l p l q j ) l j x u h $ f w l y h 3 r z h u ' r z q ( q w u \ d q g ( [ l w ) l j x u h 3 u h f k d u j h 3 r z h u ' r z q ) d v w ( [ l w 0 r g h ( q w u \ d q g ( [ l w ) l j x u h 3 u h f k d u j h 3 r z h u ' r z q 6 o r z ( [ l w 0 r g h ( q w u \ d q g ( [ l w ) l j x u h 3 r z h u ' r z q ( q w u \ $ i w h u 5 ( $ ' r u 5 ( $ ' z l w k $ x w r 3 u h f k d u j h 5 ' $ 3 ) l j x u h 3 r z h u ' r z q ( q w u \ $ i w h u : 5 , 7 ( ) l j x u h 3 r z h u ' r z q ( q w u \ $ i w h u : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h : 5 $ 3 ) l j x u h 5 ( ) 5 ( 6 + w r 3 r z h u ' r z q ( q w u \ ) l j x u h $ & 7 , 9 $ 7 ( w r 3 r z h u ' r z q ( q w u \ ) l j x u h 3 5 ( & + $ 5 * ( w r 3 r z h u ' r z q ( q w u \ ) l j x u h 0 5 6 & r p p d q g w r 3 r z h u ' r z q ( q w u \ ) l j x u h 3 r z h u ' r z q ( [ l w w r 5 h i u h v k w r 3 r z h u ' r z q ( q w u \ logic devices incorporated www.logicdevices.com 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product ) l j x u h 5 ( 6 ( 7 6 h t x h q f h ) l j x u h 2 q ' l h 7 h u p l q d w l r q ) l j x u h ' \ q d p l f 2 ' 7 2 ' 7 $ v v h u w h g % h i r u h d q g $ i w h u w k h : 5 , 7 ( % & ) l j x u h ' \ q d p l f 2 ' 7 : l w k r x w : 5 , 7 ( & r p p d q g ) l j x u h ' \ q d p l f 2 ' 7 2 ' 7 3 l q $ v v h u w h g 7 r j h w k h u z l w k : 5 , 7 ( & r p p d q g i r u & o r f n & \ f o h v % / ) l j x u h ' \ q d p l f 2 ' 7 2 ' 7 3 l q $ v v h u w h g z l w k : 5 , 7 ( & r p p d q g i r u & o r f n & \ f o h v % & ) l j x u h ' \ q d p l f 2 ' 7 2 ' 7 3 l q $ v v h u w h g z l w k : 5 , 7 ( & r p p d q g i r u & o r f n f \ f o h v % & ) l j x u h 6 \ q f k u r q r x v 2 ' 7 ) l j x u h 6 \ q f k u r q r x v 2 ' 7 % & ) l j x u h 2 ' 7 ' x u l q j 5 ( $ ' v ) l j x u h $ v \ q f k u r q r x v 2 ' 7 w l p l q j z l w k ) d v w 2 ' 7 7 u d q v l w l r q ) l j x u h 6 \ q f k u r q r x v w r $ v \ q f k u r q r x v 7 u d q v l w l r q ' x u l q j 3 u h f k d u j h 3 r z h u ' r z q ' / / 2 i i ( q w u \ ) l j x u h $ v \ q f k u r q r x v w r 6 \ q f k u r q r x v 7 u d q v l w l r q ' x u l q j 3 u h f k d u j h 3 r z h u ' r z q ' / / 2 i i ( [ l w ) l j x u h 7 u d q v l w l r q 3 h u l r g i r u 6 k r u w & . ( / 2 : & \ f o h v z l w k ( q w u \ d q g ( [ l w 3 h u l r g 2 y h u o d s s l q j ) l j x u h 7 u d q v l w l r q 3 h u l r g i r u 6 k r u w & . ( + , * + & \ f o h v z l w k ( q w u \ d q g ( [ l w 3 h u l r g 2 y h u o d s s l q j logic devices incorporated www.logicdevices.com 158 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product list of tables 7 d e o h $ g g u h v v l q j 7 d e o h % d o o 6 l j q d o / r f d w l r q d q g ' h v f u l s w l r q 7 d e o h $ e v r o x w h 0 d [ l p x p 5 d w l q j v 7 d e o h , q s x w 2 x w s x w & d s d f l w d q f h 7 d e o h 7 l p l q j 3 d u d p h w h u v i r u , ' ' 0 h d v x u h p h q w v & o r f n 8 q l w v 7 d e o h , dd0 0 h d v x u h p h q w / r r s 7 d e o h , dd1 0 h d v x u h p h q w / r r s 7 d e o h , dd 0 h d v x u h p h q w & r q g l w l r q v i r u 3 r z h u ' r z q & x u u h q w v 7 d e o h , dd2n /i dd3n 0 h d v x u h p h q w / r r s 7 d e o h , dd2nt 0 h d v x u h p h q w / r r s 7 d e o h , dd4r 0 h d v x u h p h q w / r r s 7 d e o h , ' ' : 0 h d v x u h p h q w / r r s 7 d e o h , dd5b 0 h d v x u h p h q w / r r s 7 d e o h , dd 0 h d v x u h p h q w / r r s 7 d e o h , ' ' 0 h d v x u h p h q w / r r s 7 d e o h , dd 0 d [ l p x p / l p l w v 7 d e o h ' & ( o h f w u l f d o & k d u d f w h u l v w l f v d q g 2 s h u d w l q j & r q g l w l r q v 7 d e o h ' & ( o h f w u l f d o & k d u d f w h u l v w l f v d q g , q s x w & r q g l w l r q v 7 d e o h , q s x w 6 z l w f k l q j & r q g l w l r q v 7 d e o h & r q w u r o d q g $ g g u h v v 3 l q v 7 d e o h & o r f n ' d w d 6 w u r e h d q g 0 d v n 3 l q v 7 d e o h ' l i i h u h q w l d o , q s x w 2 s h u d w l q j & r q g l w l r q v & . [ & . [ ? ' 4 6 [ d q g ' 4 6 [ ? 7 d e o h ' l i i h u h q w l d o , q s x w 2 s h u d w l q j & r q g l w l r q v t ' 9 $ & i r u & . [ & . [ ? ' 4 6 [ d q g ' 4 6 [ ? 7 d e o h 6 l q j o h ( q g h g , q s x w 6 o h z 5 d w h 7 d e o h ' l i i h u h q w l d o , q s x w 6 o h z 5 d w h ' h i l q l w l r q 7 d e o h 2 q ' l h 7 h u p l q d w l r q ' & ( o h f w u l f d o & k d u d f w h u l v w l f v 7 d e o h 5 tt ( i i h f w l y h , p s h g d q f h v 7 d e o h 2 ' 7 6 h q v l w l y l w \ ' h i l q l w l r q 7 d e o h 2 ' 7 7 h p s h u d w x u h 9 r o w d j h 6 h q v l w l y l w \ 7 d e o h 2 ' 7 7 l p l q j ' h i l q l w l r q v 7 d e o h 5 h i h u h q f h 6 h w w l q j v i r u 2 ' 7 7 l p l q j 0 h d v x u h p h q w v 7 d e o h : ' u l y h u , p s h g d q f h & k d u d f w h u l v w l f v 7 d e o h : ' u l y h u 3 x o o 8 s d q g 3 x o o ' r z q , p s h g d q f h & d o f x o d w l r q v 7 d e o h : driver i 2 + /i ol & k d u d f w h u l v w l f v 9 dd 9 ddq 9 7 d e o h : driver i 2 + /i ol & k d u d f w h u l v w l f v 9 dd 9 ddq 9 7 d e o h : driver i 2 + /i ol & k d u d f w h u l v w l f v 9 dd 9 ddq 9 7 d e o h : 2 x w s x w ' u l y h u 6 h q v l w l y l w \ ' h i l q l w l r q 7 d e o h : 2 x w s x w ' u l y h u 9 r o w d j h d q g 7 h p s h u d w x u h 6 h q v l w l y l w \ 7 d e o h : ' u l y h u , p s h g d q f h & k d u d f w h u l v w l f v 7 d e o h : 2 x w s x w ' u l y h u 6 h q v l w l y l w \ ' h i l q l w l r q 7 d e o h : 2 x w s x w ' u l y h u 9 r o w d j h d q g 7 h p s h u d w x u h 6 h q v l w l y l w \ 7 d e o h 6 l q j o h ( q g h g 2 x w s x w ' u l y h u & k d u d f w h u l v w l f v 7 d e o h ' l i i h u h q w l d o 2 x w s x w ' u l y h u & k d u d f w h u l v w l f v 7 d e o h 6 l q j o h ( q g h g 2 x w s x w 6 o h z 5 d w h 7 d e o h ' l i i h u h q w l d o 2 x w s x w 6 o h z u d w h ' h i l q l w l r q 7 d e o h 6 s h h g % l q v 7 d e o h ( o h f w u l f d o & k d u d f w h u l v w l f v d q g $ & 2 s h u d w l q j & r q g l w l r q v 7 d e o h & r p p d q g d q g $ g g u h v v 6 h w x s d q g + r o g 9 d o x h v 5 h i h u h q f h g d w 9 q v $ & ' & % d v h g logic devices incorporated www.logicdevices.com 159 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product 7 d e o h ' h u d w l q j 9 d o x h v i r u t is/ t , + $ & ' & % d v h g 7 d e o h ' h u d w l q j 9 d o x h v i r u t is/ t , + $ & ' & % d v h g 7 d e o h 0 l q l p x p 5 h t x l u h g 7 l p h t 9 $ & d e r y h 9 , + $ & i r u d 9 d o l g 7 u d q v l w l r q 7 d e o h ' d w d 6 h w x s d q g + r o g 9 d o x h v d w 9 q v ' 4 6 [ ' 4 6 [ ? d w 9 q v $ & ' & e d v h g 7 d e o h ' h u d w l q j 9 d o x h i r u t ds/ t ' + $ & ' & % d v h g 7 d e o h ' h u d w l q j 9 d o x h i r u t ds/ t ' + $ & ' & % d v h g 7 d e o h 5 h t x l u h g 7 l p h t 9 $ & $ e r y h 9 , + $ & % h o r z 9 , / > $ & @ ) r u d 9 d o l g 7 u d q v l w l r q 7 d e o h 7 u x w k 7 d e o h & r p p d q g 7 d e o h 7 u x w k 7 d e o h & . ( 7 d e o h 5 h d g & r p p d q g 6 x p p d u \ 7 d e o h : u l w h & r p p d q g 6 x p p d u \ 7 d e o h % x u v w 2 u g h u 7 d e o h % x u v w 2 u g h u 7 d e o h % x u v w 2 u g h u 7 d e o h 6 ( / ) 5 ( ) 5 ( 6 + 7 h p s h u d w x u h d q g $ 8 7 2 6 ( / ) 5 ( ) 5 ( 6 + ' h v f u l s w l r q 7 d e o h 6 ( / ) 5 ( ) 5 ( 6 + 0 r g h 6 x p p d u \ 7 d e o h & 2 0 0 $ 1 ' w r 3 2 : ( 5 ' 2 : 1 ( q w u \ 3 d u d p h w h u v 7 d e o h 3 2 : ( 5 ' 2 : 1 0 r g h v 7 d e o h 3 2 : ( 5 ' 2 : 1 0 r g h v 7 d e o h 2 ' 7 3 d u d p h w h u 7 d e o h ' \ q d p l f 2 ' 7 6 s h f l i l f 3 d u d p h w h u v 7 d e o h 0 2 ' ( 5 ( * , 6 7 ( 5 6 i r u 5 tt_nom 144 7 d e o h 0 2 ' ( 5 ( * , 6 7 ( 5 6 i r u 5 7 7 : 5 144 7 d e o h 7 , 0 , 1 * ' , $ * 5 $ 0 6 i r u ' < 1 $ 0 , & 2 ' 7 7 d e o h 6 < 1 & + 5 2 1 2 8 6 2 ' 7 3 d u d p h w h u v 7 d e o h $ 6 < 1 & + 5 2 1 2 8 6 2 ' 7 w l p l q j 3 d u d p h w h u v i r u $ o o 6 s h h g % l q v 7 d e o h 2 ' 7 3 d u d p h w h u v i r u 3 2 : ( 5 ' 2 : 1 ' / / 2 i i ( q w u \ d q g ( [ l w 7 u d q v l w l r q 3 h u l r g / 2 * , & ' h y l f h v , q f r u s r u d w h g u h v h u y h v w k h u l j k w w r p d n h f r u u h f w l r q v p r g l i l f d w l r q v h q k d q f h p h q w v l p s u r y h p h q w v d q g r w k h u f k d q j h v w r l w v s u r g x f w v d q g v h u y l f h v d w d q \ w l p h d q g w r g l v f r q w l q x h d q \ s u r g x f w r u v h u y l f h z l w k r x w q r w l f h & x v w r p h u v v k r x o g r e w d l q w k h o d w h v w u h o h y d q w l q i r u p d - w l r q e h i r u h s o d f l q j r u g h u v d q g v k r x o g y h u l i \ w k d w v x f k l q i r u p d w l r q l v f x u u h q w d q g f r p s o h w h / 2 * , & ' h y l f h v g r h v q r w d v v x p h d q \ o l d e l o l w \ d u l v l q j r x w r i w k h d s s o l f d w l r q r u x v h r i d q \ s u r g x f w r u f l u f x l w g h v f u l e h g k h u h l q , q q r h y h q w v k d o o d q \ o l d e l o l w \ h [ f h h g w k h s u r g x f w s x u f k d v h s u l f h / 2 * , & ' h y l f h v e h o l h y h v w k h l q i r u p d w l r q f r q w d l q h g k h u h l q l v d f f x u d w h k r z h y h u l w l v q r w o l d e o h i r u l q d g y h u w h q w h u u r u v , q i r u p d w l r q v x e m h f w w r f k d q j h z l w k r x w q r w l f h / 2 * , & ' h y l f h v d v v x p h v q r o l d e l o l w \ i r u x v h r i l w v s u r g x f w v l q p l v v l r q f u l w l f d o r u o l i h v x s s r u w d s s o l f d w l r q v 3 u r g x f w v r i / 2 * , & ' h y l f h v d u h q r w z d u u d q w h g q r u l q w h q g h g w r e h x v h g i r u p h g l f d o o l i h v x s s r u w o l i h v d y l q j f u l w l f d o f r q w u r o r u v d i h w \ d s s o l f d w l r q v x q o h v v s x u v x d q w w r d q h [ s u h v v z u l w w h q d j u h h p h q w z l w k / 2 * , & ' h y l f h v ) x u w k h u p r u h / 2 * , & ' h y l f h v g r h v q r w d x w k r u l ] h l w v s u r g x f w v i r u x v h d v f u l w l f d o f r p s r q h q w v l q o l i h v x s s r u w v \ v w h p v z k h u h d p d o i x q f w l r q r u i d l o x u h p d \ u h d v r q d e o \ e h h [ s h f w h g w r u h v x o w l q v l j q l i l f d q w l q m x u \ w r w k h x v h u logic devices incorporated www.logicdevices.com 160 18-20 gb, ddr3, 256 m x 72/80 integrated module L9D3256M72SBG2 preliminary information l9d3256m80sbg2 july 24, 2013 lds-l9d3256mxxsbg2 rev b high performance, integrated memory module product r evision h istory revision engineer issue date description of change $ b , 1 , 7 , $ 7 ( 8 s g d w h g w d e o h v w r l q f o x g h g d w d i r u 9 ' ' 9 . + / % l o o 9 r o ] |
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